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AMDGPU: Fix assert on physreg MUBUF rsrc operand #120815

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Merged
merged 1 commit into from
Jan 7, 2025
Merged

AMDGPU: Fix assert on physreg MUBUF rsrc operand #120815

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3 changes: 1 addition & 2 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6866,9 +6866,8 @@ SIInstrInfo::legalizeOperands(MachineInstr &MI,
AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
if (RsrcIdx != -1) {
MachineOperand *Rsrc = &MI.getOperand(RsrcIdx);
if (Rsrc->isReg() && !RI.isSGPRClass(MRI.getRegClass(Rsrc->getReg()))) {
if (Rsrc->isReg() && !RI.isSGPRReg(MRI, Rsrc->getReg()))
isRsrcLegal = false;
}
}

// The operands are legal.
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23 changes: 23 additions & 0 deletions llvm/test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll
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@@ -0,0 +1,23 @@
; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -O0 2> %t.err < %s | FileCheck %s
; RUN: FileCheck -check-prefix=ERR %s < %t.err

; FIXME: This error will be fixed by supporting arbitrary divergent
; dynamic allocas by performing a wave umax of the size.

; ERR: error: <unknown>:0:0: in function move_to_valu_assert_srd_is_physreg_swdev503538 i32 (ptr addrspace(1)): illegal VGPR to SGPR copy

; CHECK: ; illegal copy v0 to s32

define i32 @move_to_valu_assert_srd_is_physreg_swdev503538(ptr addrspace(1) %ptr) {
entry:
%idx = load i32, ptr addrspace(1) %ptr, align 4
%zero = extractelement <4 x i32> zeroinitializer, i32 %idx
%alloca = alloca [2048 x i8], i32 %zero, align 8, addrspace(5)
%ld = load i32, ptr addrspace(5) %alloca, align 8
call void @llvm.memset.p5.i32(ptr addrspace(5) %alloca, i8 0, i32 2048, i1 false)
ret i32 %ld
}

declare void @llvm.memset.p5.i32(ptr addrspace(5) nocapture writeonly, i8, i32, i1 immarg) #0

attributes #0 = { nocallback nofree nounwind willreturn memory(argmem: write) }
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