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[AArch64][SME2] Extend getRegAllocationHints for ZPRStridedOrContiguousReg #119865

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Merged
merged 6 commits into from
Dec 19, 2024
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[AArch64][SME2] Extend getRegAllocationHints for ZPRStridedOrContiguousReg #119865

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8f466f8
Add SME2 dot tests using the SVE calling convention
kmclaughlin-arm Dec 13, 2024
53e6242
[AArch64][SME2] Extend getRegAllocationHints for ZPRStridedOrContiguo…
kmclaughlin-arm Dec 13, 2024
b49fa70
- Replaced HintStrided with any_of
kmclaughlin-arm Dec 17, 2024
1ac1992
- Replace uses of undef with poison in sme2 dot intrinsic tests
kmclaughlin-arm Dec 17, 2024
70b5317
- Combine if conditions in getRegAllocationHints
kmclaughlin-arm Dec 18, 2024
52f2bd3
- Reword comments in getRegAllocationHints
kmclaughlin-arm Dec 18, 2024
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32 changes: 32 additions & 0 deletions llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1099,6 +1099,38 @@ bool AArch64RegisterInfo::getRegAllocationHints(
const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
const MachineRegisterInfo &MRI = MF.getRegInfo();

// Since the SVE calling convention preserves registers Z8-Z23, there are no
// ZPR2Strided or ZPR4Strided registers which do not overlap with the
// callee-saved registers. These will be pushed to the back of the allocation
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nit:

Suggested change
// Since the SVE calling convention preserves registers Z8-Z23, there are no
// ZPR2Strided or ZPR4Strided registers which do not overlap with the
// callee-saved registers. These will be pushed to the back of the allocation
// The SVE calling convention preserves registers Z8-Z23. As a result, there are no
// ZPR2Strided or ZPR4Strided registers that do not overlap with the
// callee-saved registers and so by default these will be pushed to the back of the allocation

// order for the ZPRStridedOrContiguous classes.
// However, if any of the instructions which define VirtReg are
// ZPRStridedOrContiguous registers used by a FORM_TRANSPOSED_REG_TUPLE
// pseudo, it will likely be better to try assigning a strided register
// anyway to avoid extra copy instructions.
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nit:

Suggested change
// However, if any of the instructions which define VirtReg are
// ZPRStridedOrContiguous registers used by a FORM_TRANSPOSED_REG_TUPLE
// pseudo, it will likely be better to try assigning a strided register
// anyway to avoid extra copy instructions.
// If any of the instructions which define VirtReg are
// used by the FORM_TRANSPOSED_REG_TUPLE
// pseudo, we actually want to favour reducing copy instructions over reducing the number of clobbered callee-save registers, so we add the registers as a hint.

(+clang-format)

unsigned RegID = MRI.getRegClass(VirtReg)->getID();
// Look through uses of the register for FORM_TRANSPOSED_REG_TUPLE.
if ((RegID == AArch64::ZPR2StridedOrContiguousRegClassID ||
RegID == AArch64::ZPR4StridedOrContiguousRegClassID) &&
any_of(MRI.use_nodbg_instructions(VirtReg), [](const MachineInstr &Use) {
return Use.getOpcode() ==
AArch64::FORM_TRANSPOSED_REG_TUPLE_X2_PSEUDO ||
Use.getOpcode() == AArch64::FORM_TRANSPOSED_REG_TUPLE_X4_PSEUDO;
})) {
// Push the list of 2/4 ZPRStrided registers to Hints to ensure we try to
// allocate these first.
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nit: can be removed, since this is covered by the comment above.

const TargetRegisterClass *StridedRC =
RegID == AArch64::ZPR2StridedOrContiguousRegClassID
? &AArch64::ZPR2StridedRegClass
: &AArch64::ZPR4StridedRegClass;

for (MCPhysReg Reg : Order)
if (StridedRC->contains(Reg))
Hints.push_back(Reg);

return TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF,
VRM);
}

for (MachineInstr &MI : MRI.def_instructions(VirtReg)) {
if (MI.getOpcode() != AArch64::FORM_TRANSPOSED_REG_TUPLE_X2_PSEUDO &&
MI.getOpcode() != AArch64::FORM_TRANSPOSED_REG_TUPLE_X4_PSEUDO)
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