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[RISCV][GISel] Support nxv16p0 for RV32. #101573

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Aug 15, 2024
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[RISCV][GISel] Support nxv16p0 for RV32. #101573

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234af49
[RISCV][GISel] Support nxv16p0 for RV32.
topperc Aug 1, 2024
d1c374f
fixup! remove IR from new tests.
topperc Aug 8, 2024
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7 changes: 5 additions & 2 deletions llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -74,7 +74,9 @@ static LegalityPredicate typeIsLegalPtrVec(unsigned TypeIdx,
LegalityPredicate P = [=, &ST](const LegalityQuery &Query) {
return ST.hasVInstructions() &&
(Query.Types[TypeIdx].getElementCount().getKnownMinValue() != 1 ||
ST.getELen() == 64);
ST.getELen() == 64) &&
(Query.Types[TypeIdx].getElementCount().getKnownMinValue() != 16 ||
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@michaelmaitland michaelmaitland Aug 9, 2024

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Can you help me understand this check?

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@topperc topperc Aug 9, 2024

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We only support a 16 element pointer vector when the element size is 32. If the pointer size is 64, then nxv16p0 should not be legal.

Query.Types[TypeIdx].getScalarSizeInBits() == 32);
};
return all(typeInSet(TypeIdx, PtrVecTys), P);
}
Expand Down Expand Up @@ -127,6 +129,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
const LLT nxv2p0 = LLT::scalable_vector(2, p0);
const LLT nxv4p0 = LLT::scalable_vector(4, p0);
const LLT nxv8p0 = LLT::scalable_vector(8, p0);
const LLT nxv16p0 = LLT::scalable_vector(16, p0);

using namespace TargetOpcode;

Expand All @@ -137,7 +140,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
nxv32s16, nxv1s32, nxv2s32, nxv4s32, nxv8s32, nxv16s32,
nxv1s64, nxv2s64, nxv4s64, nxv8s64};

auto PtrVecTys = {nxv1p0, nxv2p0, nxv4p0, nxv8p0};
auto PtrVecTys = {nxv1p0, nxv2p0, nxv4p0, nxv8p0, nxv16p0};

getActionDefinitionsBuilder({G_ADD, G_SUB, G_AND, G_OR, G_XOR})
.legalFor({s32, sXLen})
Expand Down
79 changes: 79 additions & 0 deletions llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-load-rv32.mir
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Original file line number Diff line number Diff line change
@@ -0,0 +1,79 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s

---
name: vload_nxv1ptr
body: |
bb.1:
liveins: $x10

; CHECK-LABEL: name: vload_nxv1ptr
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 1 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x p0>))
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x p0>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(p0) = COPY $x10
%1:_(<vscale x 1 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 1 x p0>), align 4)
$v8 = COPY %1(<vscale x 1 x p0>)
PseudoRET implicit $v8

...
---
name: vload_nxv2ptr
body: |
bb.1:
liveins: $x10

; CHECK-LABEL: name: vload_nxv2ptr
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x p0>))
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x p0>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(p0) = COPY $x10
%1:_(<vscale x 2 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 2 x p0>), align 8)
$v8 = COPY %1(<vscale x 2 x p0>)
PseudoRET implicit $v8

...
---
name: vload_nxv8ptr
body: |
bb.1:
liveins: $x10

; CHECK-LABEL: name: vload_nxv8ptr
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x p0>))
; CHECK-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 8 x p0>)
; CHECK-NEXT: PseudoRET implicit $v8m4
%0:_(p0) = COPY $x10
%1:_(<vscale x 8 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 8 x p0>), align 32)
$v8m4 = COPY %1(<vscale x 8 x p0>)
PseudoRET implicit $v8m4

...
---
name: vload_nxv16ptr
body: |
bb.1:
liveins: $x10

; CHECK-LABEL: name: vload_nxv16ptr
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x p0>))
; CHECK-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 16 x p0>)
; CHECK-NEXT: PseudoRET implicit $v8m8
%0:_(p0) = COPY $x10
%1:_(<vscale x 16 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 16 x p0>), align 64)
$v8m4 = COPY %1(<vscale x 16 x p0>)
PseudoRET implicit $v8m8

...
60 changes: 60 additions & 0 deletions llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-load-rv64.mir
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Original file line number Diff line number Diff line change
@@ -0,0 +1,60 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s

---
name: vload_nxv1ptr
body: |
bb.1:
liveins: $x10

; CHECK-LABEL: name: vload_nxv1ptr
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 1 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x p0>))
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x p0>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(p0) = COPY $x10
%1:_(<vscale x 1 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 1 x p0>), align 8)
$v8 = COPY %1(<vscale x 1 x p0>)
PseudoRET implicit $v8

...
---
name: vload_nxv2ptr
body: |
bb.1:
liveins: $x10

; CHECK-LABEL: name: vload_nxv2ptr
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x p0>))
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x p0>)
; CHECK-NEXT: PseudoRET implicit $v8m2
%0:_(p0) = COPY $x10
%1:_(<vscale x 2 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 2 x p0>), align 16)
$v8 = COPY %1(<vscale x 2 x p0>)
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@jiahanxie353 jiahanxie353 Aug 4, 2024

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I'm wondering, should we bitcast nxvNp0 to nxvNs32 and nxvNs64 for rv32 and rv64, respectively, during legalization?
For this example, should we have:

%1:_(<vscale x 2 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 2 x p0>) from %ir.pa, align 16)
%2:_(<vscale x 2 x s64>) = G_BITCAST %1(<vscale x 2 x p0>)
$v8 = COPY %2(<vscale x 2 x s64>)

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@topperc topperc Aug 4, 2024

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I don't think so. The user of the load is likely to be something that needs a vector of pointer.

PseudoRET implicit $v8m2

...
---
name: vload_nxv8ptr
body: |
bb.1:
liveins: $x10

; CHECK-LABEL: name: vload_nxv8ptr
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x p0>))
; CHECK-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 8 x p0>)
; CHECK-NEXT: PseudoRET implicit $v8m8
%0:_(p0) = COPY $x10
%1:_(<vscale x 8 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 8 x p0>), align 64)
$v8m4 = COPY %1(<vscale x 8 x p0>)
PseudoRET implicit $v8m8

...
72 changes: 0 additions & 72 deletions llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-load.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -203,21 +203,6 @@
ret <vscale x 2 x i64> %va
}

define <vscale x 1 x ptr> @vload_nxv1ptr(ptr %pa) #0 {
%va = load <vscale x 1 x ptr>, ptr %pa, align 4
ret <vscale x 1 x ptr> %va
}

define <vscale x 2 x ptr> @vload_nxv2ptr(ptr %pa) #0 {
%va = load <vscale x 2 x ptr>, ptr %pa, align 8
ret <vscale x 2 x ptr> %va
}

define <vscale x 8 x ptr> @vload_nxv8ptr(ptr %pa) #0 {
%va = load <vscale x 8 x ptr>, ptr %pa, align 32
ret <vscale x 8 x ptr> %va
}

attributes #0 = { "target-features"="+v" }

...
Expand Down Expand Up @@ -984,60 +969,3 @@ body: |
PseudoRET implicit $v8m2

...
---
name: vload_nxv1ptr
body: |
bb.1 (%ir-block.0):
liveins: $x10

; CHECK-LABEL: name: vload_nxv1ptr
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 1 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x p0>) from %ir.pa)
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x p0>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(p0) = COPY $x10
%1:_(<vscale x 1 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 1 x p0>) from %ir.pa)
$v8 = COPY %1(<vscale x 1 x p0>)
PseudoRET implicit $v8

...
---
name: vload_nxv2ptr
body: |
bb.1 (%ir-block.0):
liveins: $x10

; CHECK-LABEL: name: vload_nxv2ptr
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x p0>) from %ir.pa)
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x p0>)
; CHECK-NEXT: PseudoRET implicit $v8
%0:_(p0) = COPY $x10
%1:_(<vscale x 2 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 2 x p0>) from %ir.pa)
$v8 = COPY %1(<vscale x 2 x p0>)
PseudoRET implicit $v8

...
---
name: vload_nxv8ptr
body: |
bb.1 (%ir-block.0):
liveins: $x10

; CHECK-LABEL: name: vload_nxv8ptr
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x p0>) from %ir.pa)
; CHECK-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 8 x p0>)
; CHECK-NEXT: PseudoRET implicit $v8m4
%0:_(p0) = COPY $x10
%1:_(<vscale x 8 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 8 x p0>) from %ir.pa)
$v8m4 = COPY %1(<vscale x 8 x p0>)
PseudoRET implicit $v8m4

...
79 changes: 79 additions & 0 deletions llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-store-rv32.mir
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Original file line number Diff line number Diff line change
@@ -0,0 +1,79 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s

---
name: vstore_nx1ptr
body: |
bb.1:
liveins: $v8, $x10

; CHECK-LABEL: name: vstore_nx1ptr
; CHECK: liveins: $v8, $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x p0>) = COPY $v8
; CHECK-NEXT: G_STORE [[COPY1]](<vscale x 1 x p0>), [[COPY]](p0) :: (store (<vscale x 1 x p0>))
; CHECK-NEXT: PseudoRET
%0:_(p0) = COPY $x10
%1:_(<vscale x 1 x p0>) = COPY $v8
G_STORE %1(<vscale x 1 x p0>), %0(p0) :: (store (<vscale x 1 x p0>), align 4)
PseudoRET

...
---
name: vstore_nx2ptr
body: |
bb.1:
liveins: $x10, $v8

; CHECK-LABEL: name: vstore_nx2ptr
; CHECK: liveins: $x10, $v8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x p0>) = COPY $v8
; CHECK-NEXT: G_STORE [[COPY1]](<vscale x 2 x p0>), [[COPY]](p0) :: (store (<vscale x 2 x p0>))
; CHECK-NEXT: PseudoRET
%0:_(p0) = COPY $x10
%1:_(<vscale x 2 x p0>) = COPY $v8
G_STORE %1(<vscale x 2 x p0>), %0(p0) :: (store (<vscale x 2 x p0>), align 8)
PseudoRET

...
---
name: vstore_nx8ptr
body: |
bb.1:
liveins: $x10, $v8m4

; CHECK-LABEL: name: vstore_nx8ptr
; CHECK: liveins: $x10, $v8m4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x p0>) = COPY $v8m4
; CHECK-NEXT: G_STORE [[COPY1]](<vscale x 8 x p0>), [[COPY]](p0) :: (store (<vscale x 8 x p0>))
; CHECK-NEXT: PseudoRET
%0:_(p0) = COPY $x10
%1:_(<vscale x 8 x p0>) = COPY $v8m4
G_STORE %1(<vscale x 8 x p0>), %0(p0) :: (store (<vscale x 8 x p0>), align 32)
PseudoRET

...
---
name: vstore_nx16ptr
body: |
bb.1:
liveins: $x10, $v8m8

; CHECK-LABEL: name: vstore_nx16ptr
; CHECK: liveins: $x10, $v8m8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x p0>) = COPY $v8m8
; CHECK-NEXT: G_STORE [[COPY1]](<vscale x 16 x p0>), [[COPY]](p0) :: (store (<vscale x 8 x p0>), align 64)
; CHECK-NEXT: PseudoRET
%0:_(p0) = COPY $x10
%1:_(<vscale x 16 x p0>) = COPY $v8m8
G_STORE %1(<vscale x 16 x p0>), %0(p0) :: (store (<vscale x 8 x p0>), align 64)
PseudoRET

...
60 changes: 60 additions & 0 deletions llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-store-rv64.mir
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Original file line number Diff line number Diff line change
@@ -0,0 +1,60 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s

---
name: vstore_nx1ptr
body: |
bb.1:
liveins: $v8, $x10

; CHECK-LABEL: name: vstore_nx1ptr
; CHECK: liveins: $v8, $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x p0>) = COPY $v8
; CHECK-NEXT: G_STORE [[COPY1]](<vscale x 1 x p0>), [[COPY]](p0) :: (store (<vscale x 1 x p0>))
; CHECK-NEXT: PseudoRET
%0:_(p0) = COPY $x10
%1:_(<vscale x 1 x p0>) = COPY $v8
G_STORE %1(<vscale x 1 x p0>), %0(p0) :: (store (<vscale x 1 x p0>), align 8)
PseudoRET

...
---
name: vstore_nx2ptr
body: |
bb.1:
liveins: $x10, $v8m2

; CHECK-LABEL: name: vstore_nx2ptr
; CHECK: liveins: $x10, $v8m2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x p0>) = COPY $v8m2
; CHECK-NEXT: G_STORE [[COPY1]](<vscale x 2 x p0>), [[COPY]](p0) :: (store (<vscale x 2 x p0>))
; CHECK-NEXT: PseudoRET
%0:_(p0) = COPY $x10
%1:_(<vscale x 2 x p0>) = COPY $v8m2
G_STORE %1(<vscale x 2 x p0>), %0(p0) :: (store (<vscale x 2 x p0>), align 16)
PseudoRET

...
---
name: vstore_nx8ptr
body: |
bb.1:
liveins: $x10, $v8m8

; CHECK-LABEL: name: vstore_nx8ptr
; CHECK: liveins: $x10, $v8m8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x p0>) = COPY $v8m8
; CHECK-NEXT: G_STORE [[COPY1]](<vscale x 8 x p0>), [[COPY]](p0) :: (store (<vscale x 8 x p0>))
; CHECK-NEXT: PseudoRET
%0:_(p0) = COPY $x10
%1:_(<vscale x 8 x p0>) = COPY $v8m8
G_STORE %1(<vscale x 8 x p0>), %0(p0) :: (store (<vscale x 8 x p0>), align 64)
PseudoRET

...
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