Missed optimization: extractps optimizes better than pshufd+movd

[Alcaro]

#include <emmintrin.h>

__m128i b;

int square() {
    if (_mm_cvtsi128_si64(b) == 0)
        return 0;
    __m128i c = _mm_shuffle_epi32(b, 238);
    return _mm_cvtsi128_si32(c);
}

Compile with -O2, and with -O2 -msse4.1.

Expected result: Either same both times, or a SSE4.1 instruction in the output.

Actual:

_Z6squarev:                             # @_Z6squarev
        xor     ecx, ecx
        cmp     qword ptr [rip + b], 0
        pshufd  xmm0, xmmword ptr [rip + b], 238 # xmm0 = mem[2,3,2,3]
        movd    eax, xmm0
        cmove   eax, ecx
        ret
b:
        .zero   16

_Z6squarev:                             # @_Z6squarev
        xor     eax, eax
        cmp     qword ptr [rip + b], 0
        je      .LBB0_2
        mov     eax, dword ptr [rip + b+8]
.LBB0_2:
        ret
b:
        .zero   16

https://godbolt.org/z/4qrGvo617

(testcase reduced from an experiment to check how thoroughly I can disprove assumptions that _mm_load_si128 is atomic)

[llvmbot]

@llvm/issue-subscribers-backend-x86

Author: None (Alcaro)

```c++ #include <emmintrin.h>

__m128i b;

int square() {
if (_mm_cvtsi128_si64(b) == 0)
return 0;
__m128i c = _mm_shuffle_epi32(b, 238);
return _mm_cvtsi128_si32(c);
}

Compile with -O2, and with -O2 -msse4.1.

Expected result: Either same both times, or a SSE4.1 instruction in the output.

Actual:

_Z6squarev: # @_Z6squarev
xor ecx, ecx
cmp qword ptr [rip + b], 0
pshufd xmm0, xmmword ptr [rip + b], 238 # xmm0 = mem[2,3,2,3]
movd eax, xmm0
cmove eax, ecx
ret
b:
.zero 16

_Z6squarev: # @_Z6squarev
xor eax, eax
cmp qword ptr [rip + b], 0
je .LBB0_2
mov eax, dword ptr [rip + b+8]
.LBB0_2:
ret
b:
.zero 16

https://godbolt.org/z/4qrGvo617

(testcase reduced from an experiment to check how thoroughly I can disprove assumptions that _mm_load_si128 is atomic)
</details>

[RKSimon]

define i32 @PR85419(ptr %p0) {
  %load = load <2 x i64>, ptr %p0, align 16
  %vecext.i = extractelement <2 x i64> %load, i64 0
  %cmp = icmp eq i64 %vecext.i, 0
  %.cast = bitcast <2 x i64> %load to <4 x i32>
  %vecext.i2 = extractelement <4 x i32> %.cast, i64 2
  %retval.0 = select i1 %cmp, i32 0, i32 %vecext.i2
  ret i32 %retval.0
}

SSE41 targets are managing to (usefully) evade the oneuse limit on uses of %load