[RISCV] Scheduler description for the Rocket core

[llvmbot]

Bugzilla Link	44719
Resolution	FIXED
Resolved on	Feb 03, 2020 07:00
Version	10.0
OS	All
Blocks	#43900
Reporter	LLVM Bugzilla Contributor
CC	@asb,@zmodem,@lenary

Extended Description

Please, merge rG838a28e234e0.

[asb]

Hi Hans - we discussed this in our regular RISC-V LLVM sync-up call. The thought was that although this change is larger than I think we'd typically want in a backport request and doesn't address a particular regression, it has very little chance of causing issues (not enabled by default, not going to cause correctness problems). Additionally, because adding the scheduler info modifies quite a lot of lines in the .td files having the backport will make it easier if we need to merge any following fixes, that might otherwise have conflicts.

So I have no objection to merging, and think there may be some benefits, but obviously it's your call on whether a merge like this would be out of the norm.

[zmodem]

Sounds good to me. Cherry-picked as 4e9209a