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[AArch64][ARM] experimental.vector.reduce without FMF asserts #43945

@nikic

Description

@nikic
Bugzilla Link 44600
Resolution FIXED
Resolved on Feb 05, 2020 04:58
Version 10.0
OS Linux
Blocks #43900
CC @alex,@Arnaud-de-Grandmaison-ARM,@zmodem,@jdm,@smithp35
Fixed by commit(s) 70d345e, 1cc4f8d, 362d00e

Extended Description

define float @​test_fadd_ordered(<3 x float> %v) {
%res = call float @​llvm.experimental.vector.reduce.v2.fadd.f32.v3f32(float 0.0, <3 x float> %v)
ret float %res
}

define float @​test_fmax_unordered_nan(<4 x float> %v) {
%res = call reassoc float @​llvm.experimental.vector.reduce.fmax.v4f32(<4 x float> %v)
ret float %res
}

declare float @​llvm.experimental.vector.reduce.v2.fadd.f32.v3f32(float %start_value, <3 x float> %a)
declare float @​llvm.experimental.vector.reduce.fmax.v4f32(<4 x float> %a)

The first case asserts on both AArch64 and ARM because there is no support for legalizing VECREDUCE_STRICT. The second one asserts on AArch64 because it requires fmax reductions to be nnan.

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