Address more comments

Author: davemgreen

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -13966,22 +13966,29 @@ SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
     auto BuildZipLike = [&DAG, &dl](unsigned OpNum, SDValue OpLHS,
                                     SDValue OpRHS) {
       EVT VT = OpLHS.getValueType();
+      unsigned Opc = 0;
       switch (OpNum) {
       default:
         llvm_unreachable("Unexpected perfect shuffle opcode");
       case OP_VUZPL:
-        return DAG.getNode(AArch64ISD::UZP1, dl, VT, OpLHS, OpRHS);
+        Opc = AArch64ISD::UZP1;
+        break;
       case OP_VUZPR:
-        return DAG.getNode(AArch64ISD::UZP2, dl, VT, OpLHS, OpRHS);
+        Opc = AArch64ISD::UZP2;
+        break;
       case OP_VZIPL:
-        return DAG.getNode(AArch64ISD::ZIP1, dl, VT, OpLHS, OpRHS);
+        Opc = AArch64ISD::ZIP1;
+        break;
       case OP_VZIPR:
-        return DAG.getNode(AArch64ISD::ZIP2, dl, VT, OpLHS, OpRHS);
+        Opc = AArch64ISD::ZIP2;
+        break;
       case OP_VTRNL:
-        return DAG.getNode(AArch64ISD::TRN1, dl, VT, OpLHS, OpRHS);
+        Opc = AArch64ISD::TRN1;
+        break;
       case OP_VTRNR:
-        return DAG.getNode(AArch64ISD::TRN2, dl, VT, OpLHS, OpRHS);
+        Opc = AArch64ISD::TRN2;
       }
+      return DAG.getNode(Opc, dl, VT, OpLHS, OpRHS);
     };
     auto BuildExtractInsert64 = [&DAG, &dl](SDValue ExtSrc, unsigned ExtLane,
                                             SDValue InsSrc, unsigned InsLane) {

llvm/lib/Target/AArch64/AArch64PerfectShuffle.h

@@ -6802,13 +6802,12 @@ inline Val generatePerfectShuffle(unsigned ID, Val V1, Val V2, unsigned PFEntry,
       ExtLane = MaskElt < 2 ? MaskElt : (MaskElt - 2);
       Input = MaskElt < 2 ? V1 : V2;
       return BuildExtractInsert64(Input, ExtLane, OpLHS, RHSID & 0x3);
-    } else {
-      int MaskElt = getPFIDLane(ID, RHSID);
-      assert(MaskElt >= 0 && "Didn't expect an undef movlane index!");
-      ExtLane = MaskElt < 4 ? MaskElt : (MaskElt - 4);
-      Input = MaskElt < 4 ? V1 : V2;
-      return BuildExtractInsert32(Input, ExtLane, OpLHS, RHSID & 0x3);
     }
+    int MaskElt = getPFIDLane(ID, RHSID);
+    assert(MaskElt >= 0 && "Didn't expect an undef movlane index!");
+    ExtLane = MaskElt < 4 ? MaskElt : (MaskElt - 4);
+    Input = MaskElt < 4 ? V1 : V2;
+    return BuildExtractInsert32(Input, ExtLane, OpLHS, RHSID & 0x3);
   }
 
   Val OpLHS, OpRHS;

llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp

@@ -591,22 +591,29 @@ void applyPerfectShuffle(MachineInstr &MI, MachineRegisterInfo &MRI,
   auto BuildZipLike = [&MIB, &MRI](unsigned OpNum, Register OpLHS,
                                    Register OpRHS) {
     LLT Ty = MRI.getType(OpLHS);
+    unsigned Opc = 0;
     switch (OpNum) {
     default:
       llvm_unreachable("Unexpected perfect shuffle opcode");
     case OP_VUZPL:
-      return MIB.buildInstr(AArch64::G_UZP1, {Ty}, {OpLHS, OpRHS}).getReg(0);
+      Opc = AArch64::G_UZP1;
+      break;
     case OP_VUZPR:
-      return MIB.buildInstr(AArch64::G_UZP2, {Ty}, {OpLHS, OpRHS}).getReg(0);
+      Opc = AArch64::G_UZP2;
+      break;
     case OP_VZIPL:
-      return MIB.buildInstr(AArch64::G_ZIP1, {Ty}, {OpLHS, OpRHS}).getReg(0);
+      Opc = AArch64::G_ZIP1;
+      break;
     case OP_VZIPR:
-      return MIB.buildInstr(AArch64::G_ZIP2, {Ty}, {OpLHS, OpRHS}).getReg(0);
+      Opc = AArch64::G_ZIP2;
+      break;
     case OP_VTRNL:
-      return MIB.buildInstr(AArch64::G_TRN1, {Ty}, {OpLHS, OpRHS}).getReg(0);
+      Opc = AArch64::G_TRN1;
+      break;
     case OP_VTRNR:
-      return MIB.buildInstr(AArch64::G_TRN2, {Ty}, {OpLHS, OpRHS}).getReg(0);
+      Opc = AArch64::G_TRN2;
     }
+    return MIB.buildInstr(Opc, {Ty}, {OpLHS, OpRHS}).getReg(0);
   };
   auto BuildExtractInsert64 = [&MIB, &MRI](Register ExtSrc, unsigned ExtLane,
                                            Register InsSrc, unsigned InsLane) {