Just use buildConstant/getConstant, we know the type already

Author: davemgreen

llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

@@ -1365,23 +1365,6 @@ class MachineIRBuilder {
                                                const SrcOp &Elt,
                                                const SrcOp &Idx);
 
-  /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val, \p Elt, \p Idx
-  ///
-  /// \pre setBasicBlock or setMI must have been called.
-  /// \pre \p Res must be a generic virtual register with scalar type.
-  /// \pre \p Val must be a generic virtual register with vector type.
-  /// \pre \p Elt must be a generic virtual register with scalar type.
-  ///
-  /// \return The newly created instruction.
-  MachineInstrBuilder buildInsertVectorElementConstant(const DstOp &Res,
-                                                       const SrcOp &Val,
-                                                       const SrcOp &Elt,
-                                                       const int Idx) {
-    const TargetLowering *TLI = getMF().getSubtarget().getTargetLowering();
-    LLT IdxTy = TLI->getVectorIdxLLT(getDataLayout());
-    return buildInsertVectorElement(Res, Val, Elt, buildConstant(IdxTy, Idx));
-  }
-
   /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
   ///
   /// \pre setBasicBlock or setMI must have been called.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -13968,7 +13968,7 @@ SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
       EVT VT = OpLHS.getValueType();
       switch (OpNum) {
       default:
-        llvm_unreachable("Unexpected perfect shuffle opcode\n");
+        llvm_unreachable("Unexpected perfect shuffle opcode");
       case OP_VUZPL:
         return DAG.getNode(AArch64ISD::UZP1, dl, VT, OpLHS, OpRHS);
       case OP_VUZPR:
@@ -13995,10 +13995,10 @@ SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
       }
       SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
                                 ExtSrc.getValueType().getVectorElementType(),
-                                ExtSrc, DAG.getVectorIdxConstant(ExtLane, dl));
+                                ExtSrc, DAG.getConstant(ExtLane, dl, MVT::i64));
       SDValue Ins =
           DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtSrc.getValueType(), InsSrc,
-                      Ext, DAG.getVectorIdxConstant(InsLane, dl));
+                      Ext, DAG.getConstant(InsLane, dl, MVT::i64));
       return DAG.getBitcast(VT, Ins);
     };
     auto BuildExtractInsert32 = [&DAG, &dl](SDValue ExtSrc, unsigned ExtLane,
@@ -14010,10 +14010,10 @@ SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
       }
       SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
                                 ExtSrc.getValueType().getVectorElementType(),
-                                ExtSrc, DAG.getVectorIdxConstant(ExtLane, dl));
+                                ExtSrc, DAG.getConstant(ExtLane, dl, MVT::i64));
       SDValue Ins =
           DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtSrc.getValueType(), InsSrc,
-                      Ext, DAG.getVectorIdxConstant(InsLane, dl));
+                      Ext, DAG.getConstant(InsLane, dl, MVT::i64));
       return DAG.getBitcast(VT, Ins);
     };
     return generatePerfectShuffle<SDValue, MVT>(

llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp

@@ -593,7 +593,7 @@ void applyPerfectShuffle(MachineInstr &MI, MachineRegisterInfo &MRI,
     LLT Ty = MRI.getType(OpLHS);
     switch (OpNum) {
     default:
-      llvm_unreachable("Unexpected perfect shuffle opcode\n");
+      llvm_unreachable("Unexpected perfect shuffle opcode");
     case OP_VUZPL:
       return MIB.buildInstr(AArch64::G_UZP1, {Ty}, {OpLHS, OpRHS}).getReg(0);
     case OP_VUZPR:
@@ -619,10 +619,12 @@ void applyPerfectShuffle(MachineInstr &MI, MachineRegisterInfo &MRI,
       ExtSrc = MIB.buildBitcast(LLT::fixed_vector(2, 64), ExtSrc).getReg(0);
       InsSrc = MIB.buildBitcast(LLT::fixed_vector(2, 64), InsSrc).getReg(0);
     }
-    auto Ext = MIB.buildExtractVectorElementConstant(
-        MRI.getType(ExtSrc).getElementType(), ExtSrc, ExtLane);
-    auto Ins = MIB.buildInsertVectorElementConstant(MRI.getType(ExtSrc), InsSrc,
-                                                    Ext, InsLane);
+    auto Ext = MIB.buildExtractVectorElement(
+        MRI.getType(ExtSrc).getElementType(), ExtSrc,
+        MIB.buildConstant(LLT::scalar(64), ExtLane));
+    auto Ins = MIB.buildInsertVectorElement(
+        MRI.getType(ExtSrc), InsSrc, Ext,
+        MIB.buildConstant(LLT::scalar(64), InsLane));
     return MIB.buildBitcast(Ty, Ins).getReg(0);
   };
   auto BuildExtractInsert32 = [&MIB, &MRI](Register ExtSrc, unsigned ExtLane,
@@ -632,10 +634,12 @@ void applyPerfectShuffle(MachineInstr &MI, MachineRegisterInfo &MRI,
       ExtSrc = MIB.buildBitcast(LLT::fixed_vector(2, 32), ExtSrc).getReg(0);
       InsSrc = MIB.buildBitcast(LLT::fixed_vector(2, 32), InsSrc).getReg(0);
     }
-    auto Ext = MIB.buildExtractVectorElementConstant(
-        MRI.getType(ExtSrc).getElementType(), ExtSrc, ExtLane);
-    auto Ins = MIB.buildInsertVectorElementConstant(MRI.getType(ExtSrc), InsSrc,
-                                                    Ext, InsLane);
+    auto Ext = MIB.buildExtractVectorElement(
+        MRI.getType(ExtSrc).getElementType(), ExtSrc,
+        MIB.buildConstant(LLT::scalar(64), ExtLane));
+    auto Ins = MIB.buildInsertVectorElement(
+        MRI.getType(ExtSrc), InsSrc, Ext,
+        MIB.buildConstant(LLT::scalar(64), InsLane));
     if (MRI.getType(Ins.getReg(0)) != Ty)
       Ins = MIB.buildBitcast(Ty, Ins);
     return Ins.getReg(0);