Skip to content

Commit 1d6f9c3

Browse files
davemgreendavemgreen
committed
[AArch64][GlobalISel] Perfect Shuffles
This is a port of the existing perfect shuffle generation code from SDAG, geneticized to work for both SDAG and GISel. I wrote it a while ago and it has been sitting on my machine. It brings the codegen for certain shuffles inline and avoids the need for generating a tbl and constant pool load.
1 parent 8639b36 commit 1d6f9c3

15 files changed

+464
-351
lines changed

‎llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1365,6 +1365,23 @@ class MachineIRBuilder {
13651365
const SrcOp &Elt,
13661366
const SrcOp &Idx);
13671367

1368+
/// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val, \p Elt, \p Idx
1369+
///
1370+
/// \pre setBasicBlock or setMI must have been called.
1371+
/// \pre \p Res must be a generic virtual register with scalar type.
1372+
/// \pre \p Val must be a generic virtual register with vector type.
1373+
/// \pre \p Elt must be a generic virtual register with scalar type.
1374+
///
1375+
/// \return The newly created instruction.
1376+
MachineInstrBuilder buildInsertVectorElementConstant(const DstOp &Res,
1377+
const SrcOp &Val,
1378+
const SrcOp &Elt,
1379+
const int Idx) {
1380+
const TargetLowering *TLI = getMF().getSubtarget().getTargetLowering();
1381+
LLT IdxTy = TLI->getVectorIdxLLT(getDataLayout());
1382+
return buildInsertVectorElement(Res, Val, Elt, buildConstant(IdxTy, Idx));
1383+
}
1384+
13681385
/// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
13691386
///
13701387
/// \pre setBasicBlock or setMI must have been called.

‎llvm/lib/Target/AArch64/AArch64Combine.td‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -155,6 +155,13 @@ def shuf_to_ins: GICombineRule <
155155
(apply [{ applyINS(*${root}, MRI, B, ${matchinfo}); }])
156156
>;
157157

158+
def perfect_shuffle: GICombineRule <
159+
(defs root:$root),
160+
(match (G_SHUFFLE_VECTOR $dst, $src1, $src2, $mask):$root,
161+
[{ return matchPerfectShuffle(*${root}, MRI); }]),
162+
(apply [{ applyPerfectShuffle(*${root}, MRI, B); }])
163+
>;
164+
158165
def vashr_vlshr_imm_matchdata : GIDefMatchData<"int64_t">;
159166
def vashr_vlshr_imm : GICombineRule<
160167
(defs root:$root, vashr_vlshr_imm_matchdata:$matchinfo),
@@ -173,7 +180,8 @@ def form_duplane : GICombineRule <
173180
>;
174181

175182
def shuffle_vector_lowering : GICombineGroup<[dup, rev, ext, zip, uzp, trn, fullrev,
176-
form_duplane, shuf_to_ins]>;
183+
form_duplane, shuf_to_ins,
184+
perfect_shuffle]>;
177185

178186
// Turn G_UNMERGE_VALUES -> G_EXTRACT_VECTOR_ELT's
179187
def vector_unmerge_lowering : GICombineRule <

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 89 additions & 168 deletions
Original file line numberDiff line numberDiff line change
@@ -13507,172 +13507,6 @@ static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
1350713507
return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
1350813508
}
1350913509

13510-
/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
13511-
/// the specified operations to build the shuffle. ID is the perfect-shuffle
13512-
//ID, V1 and V2 are the original shuffle inputs. PFEntry is the Perfect shuffle
13513-
//table entry and LHS/RHS are the immediate inputs for this stage of the
13514-
//shuffle.
13515-
static SDValue GeneratePerfectShuffle(unsigned ID, SDValue V1,
13516-
SDValue V2, unsigned PFEntry, SDValue LHS,
13517-
SDValue RHS, SelectionDAG &DAG,
13518-
const SDLoc &dl) {
13519-
unsigned OpNum = (PFEntry >> 26) & 0x0F;
13520-
unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
13521-
unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
13522-
13523-
enum {
13524-
OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
13525-
OP_VREV,
13526-
OP_VDUP0,
13527-
OP_VDUP1,
13528-
OP_VDUP2,
13529-
OP_VDUP3,
13530-
OP_VEXT1,
13531-
OP_VEXT2,
13532-
OP_VEXT3,
13533-
OP_VUZPL, // VUZP, left result
13534-
OP_VUZPR, // VUZP, right result
13535-
OP_VZIPL, // VZIP, left result
13536-
OP_VZIPR, // VZIP, right result
13537-
OP_VTRNL, // VTRN, left result
13538-
OP_VTRNR, // VTRN, right result
13539-
OP_MOVLANE // Move lane. RHSID is the lane to move into
13540-
};
13541-
13542-
if (OpNum == OP_COPY) {
13543-
if (LHSID == (1 * 9 + 2) * 9 + 3)
13544-
return LHS;
13545-
assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
13546-
return RHS;
13547-
}
13548-
13549-
if (OpNum == OP_MOVLANE) {
13550-
// Decompose a PerfectShuffle ID to get the Mask for lane Elt
13551-
auto getPFIDLane = [](unsigned ID, int Elt) -> int {
13552-
assert(Elt < 4 && "Expected Perfect Lanes to be less than 4");
13553-
Elt = 3 - Elt;
13554-
while (Elt > 0) {
13555-
ID /= 9;
13556-
Elt--;
13557-
}
13558-
return (ID % 9 == 8) ? -1 : ID % 9;
13559-
};
13560-
13561-
// For OP_MOVLANE shuffles, the RHSID represents the lane to move into. We
13562-
// get the lane to move from the PFID, which is always from the
13563-
// original vectors (V1 or V2).
13564-
SDValue OpLHS = GeneratePerfectShuffle(
13565-
LHSID, V1, V2, PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
13566-
EVT VT = OpLHS.getValueType();
13567-
assert(RHSID < 8 && "Expected a lane index for RHSID!");
13568-
unsigned ExtLane = 0;
13569-
SDValue Input;
13570-
13571-
// OP_MOVLANE are either D movs (if bit 0x4 is set) or S movs. D movs
13572-
// convert into a higher type.
13573-
if (RHSID & 0x4) {
13574-
int MaskElt = getPFIDLane(ID, (RHSID & 0x01) << 1) >> 1;
13575-
if (MaskElt == -1)
13576-
MaskElt = (getPFIDLane(ID, ((RHSID & 0x01) << 1) + 1) - 1) >> 1;
13577-
assert(MaskElt >= 0 && "Didn't expect an undef movlane index!");
13578-
ExtLane = MaskElt < 2 ? MaskElt : (MaskElt - 2);
13579-
Input = MaskElt < 2 ? V1 : V2;
13580-
if (VT.getScalarSizeInBits() == 16) {
13581-
Input = DAG.getBitcast(MVT::v2f32, Input);
13582-
OpLHS = DAG.getBitcast(MVT::v2f32, OpLHS);
13583-
} else {
13584-
assert(VT.getScalarSizeInBits() == 32 &&
13585-
"Expected 16 or 32 bit shuffle elemements");
13586-
Input = DAG.getBitcast(MVT::v2f64, Input);
13587-
OpLHS = DAG.getBitcast(MVT::v2f64, OpLHS);
13588-
}
13589-
} else {
13590-
int MaskElt = getPFIDLane(ID, RHSID);
13591-
assert(MaskElt >= 0 && "Didn't expect an undef movlane index!");
13592-
ExtLane = MaskElt < 4 ? MaskElt : (MaskElt - 4);
13593-
Input = MaskElt < 4 ? V1 : V2;
13594-
// Be careful about creating illegal types. Use f16 instead of i16.
13595-
if (VT == MVT::v4i16) {
13596-
Input = DAG.getBitcast(MVT::v4f16, Input);
13597-
OpLHS = DAG.getBitcast(MVT::v4f16, OpLHS);
13598-
}
13599-
}
13600-
SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
13601-
Input.getValueType().getVectorElementType(),
13602-
Input, DAG.getVectorIdxConstant(ExtLane, dl));
13603-
SDValue Ins =
13604-
DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Input.getValueType(), OpLHS,
13605-
Ext, DAG.getVectorIdxConstant(RHSID & 0x3, dl));
13606-
return DAG.getBitcast(VT, Ins);
13607-
}
13608-
13609-
SDValue OpLHS, OpRHS;
13610-
OpLHS = GeneratePerfectShuffle(LHSID, V1, V2, PerfectShuffleTable[LHSID], LHS,
13611-
RHS, DAG, dl);
13612-
OpRHS = GeneratePerfectShuffle(RHSID, V1, V2, PerfectShuffleTable[RHSID], LHS,
13613-
RHS, DAG, dl);
13614-
EVT VT = OpLHS.getValueType();
13615-
13616-
switch (OpNum) {
13617-
default:
13618-
llvm_unreachable("Unknown shuffle opcode!");
13619-
case OP_VREV:
13620-
// VREV divides the vector in half and swaps within the half.
13621-
if (VT.getVectorElementType() == MVT::i32 ||
13622-
VT.getVectorElementType() == MVT::f32)
13623-
return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
13624-
// vrev <4 x i16> -> REV32
13625-
if (VT.getVectorElementType() == MVT::i16 ||
13626-
VT.getVectorElementType() == MVT::f16 ||
13627-
VT.getVectorElementType() == MVT::bf16)
13628-
return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
13629-
// vrev <4 x i8> -> REV16
13630-
assert(VT.getVectorElementType() == MVT::i8);
13631-
return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
13632-
case OP_VDUP0:
13633-
case OP_VDUP1:
13634-
case OP_VDUP2:
13635-
case OP_VDUP3: {
13636-
EVT EltTy = VT.getVectorElementType();
13637-
unsigned Opcode;
13638-
if (EltTy == MVT::i8)
13639-
Opcode = AArch64ISD::DUPLANE8;
13640-
else if (EltTy == MVT::i16 || EltTy == MVT::f16 || EltTy == MVT::bf16)
13641-
Opcode = AArch64ISD::DUPLANE16;
13642-
else if (EltTy == MVT::i32 || EltTy == MVT::f32)
13643-
Opcode = AArch64ISD::DUPLANE32;
13644-
else if (EltTy == MVT::i64 || EltTy == MVT::f64)
13645-
Opcode = AArch64ISD::DUPLANE64;
13646-
else
13647-
llvm_unreachable("Invalid vector element type?");
13648-
13649-
if (VT.getSizeInBits() == 64)
13650-
OpLHS = WidenVector(OpLHS, DAG);
13651-
SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, dl, MVT::i64);
13652-
return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
13653-
}
13654-
case OP_VEXT1:
13655-
case OP_VEXT2:
13656-
case OP_VEXT3: {
13657-
unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
13658-
return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
13659-
DAG.getConstant(Imm, dl, MVT::i32));
13660-
}
13661-
case OP_VUZPL:
13662-
return DAG.getNode(AArch64ISD::UZP1, dl, VT, OpLHS, OpRHS);
13663-
case OP_VUZPR:
13664-
return DAG.getNode(AArch64ISD::UZP2, dl, VT, OpLHS, OpRHS);
13665-
case OP_VZIPL:
13666-
return DAG.getNode(AArch64ISD::ZIP1, dl, VT, OpLHS, OpRHS);
13667-
case OP_VZIPR:
13668-
return DAG.getNode(AArch64ISD::ZIP2, dl, VT, OpLHS, OpRHS);
13669-
case OP_VTRNL:
13670-
return DAG.getNode(AArch64ISD::TRN1, dl, VT, OpLHS, OpRHS);
13671-
case OP_VTRNR:
13672-
return DAG.getNode(AArch64ISD::TRN2, dl, VT, OpLHS, OpRHS);
13673-
}
13674-
}
13675-
1367613510
static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
1367713511
SelectionDAG &DAG) {
1367813512
// Check to see if we can use the TBL instruction.
@@ -14096,8 +13930,95 @@ SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
1409613930
unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
1409713931
PFIndexes[2] * 9 + PFIndexes[3];
1409813932
unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
14099-
return GeneratePerfectShuffle(PFTableIndex, V1, V2, PFEntry, V1, V2, DAG,
14100-
dl);
13933+
13934+
auto BuildRev = [&DAG, &dl](SDValue OpLHS) {
13935+
EVT VT = OpLHS.getValueType();
13936+
unsigned Opcode = VT.getScalarSizeInBits() == 32 ? AArch64ISD::REV64
13937+
: VT.getScalarSizeInBits() == 16 ? AArch64ISD::REV32
13938+
: AArch64ISD::REV16;
13939+
return DAG.getNode(Opcode, dl, VT, OpLHS);
13940+
};
13941+
auto BuildDup = [&DAG, &dl](SDValue OpLHS, unsigned Lane) {
13942+
EVT VT = OpLHS.getValueType();
13943+
unsigned Opcode;
13944+
if (VT.getScalarSizeInBits() == 8)
13945+
Opcode = AArch64ISD::DUPLANE8;
13946+
else if (VT.getScalarSizeInBits() == 16)
13947+
Opcode = AArch64ISD::DUPLANE16;
13948+
else if (VT.getScalarSizeInBits() == 32)
13949+
Opcode = AArch64ISD::DUPLANE32;
13950+
else if (VT.getScalarSizeInBits() == 64)
13951+
Opcode = AArch64ISD::DUPLANE64;
13952+
else
13953+
llvm_unreachable("Invalid vector element type?");
13954+
13955+
if (VT.getSizeInBits() == 64)
13956+
OpLHS = WidenVector(OpLHS, DAG);
13957+
return DAG.getNode(Opcode, dl, VT, OpLHS,
13958+
DAG.getConstant(Lane, dl, MVT::i64));
13959+
};
13960+
auto BuildExt = [&DAG, &dl](SDValue OpLHS, SDValue OpRHS, unsigned Imm) {
13961+
EVT VT = OpLHS.getValueType();
13962+
Imm = Imm * getExtFactor(OpLHS);
13963+
return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
13964+
DAG.getConstant(Imm, dl, MVT::i32));
13965+
};
13966+
auto BuildZipLike = [&DAG, &dl](unsigned OpNum, SDValue OpLHS,
13967+
SDValue OpRHS) {
13968+
EVT VT = OpLHS.getValueType();
13969+
switch (OpNum) {
13970+
default:
13971+
llvm_unreachable("Unexpected perfect shuffle opcode\n");
13972+
case OP_VUZPL:
13973+
return DAG.getNode(AArch64ISD::UZP1, dl, VT, OpLHS, OpRHS);
13974+
case OP_VUZPR:
13975+
return DAG.getNode(AArch64ISD::UZP2, dl, VT, OpLHS, OpRHS);
13976+
case OP_VZIPL:
13977+
return DAG.getNode(AArch64ISD::ZIP1, dl, VT, OpLHS, OpRHS);
13978+
case OP_VZIPR:
13979+
return DAG.getNode(AArch64ISD::ZIP2, dl, VT, OpLHS, OpRHS);
13980+
case OP_VTRNL:
13981+
return DAG.getNode(AArch64ISD::TRN1, dl, VT, OpLHS, OpRHS);
13982+
case OP_VTRNR:
13983+
return DAG.getNode(AArch64ISD::TRN2, dl, VT, OpLHS, OpRHS);
13984+
}
13985+
};
13986+
auto BuildExtractInsert64 = [&DAG, &dl](SDValue ExtSrc, unsigned ExtLane,
13987+
SDValue InsSrc, unsigned InsLane) {
13988+
EVT VT = InsSrc.getValueType();
13989+
if (VT.getScalarSizeInBits() == 16) {
13990+
ExtSrc = DAG.getBitcast(MVT::v2f32, ExtSrc);
13991+
InsSrc = DAG.getBitcast(MVT::v2f32, InsSrc);
13992+
} else if (VT.getScalarSizeInBits() == 32) {
13993+
ExtSrc = DAG.getBitcast(MVT::v2f64, ExtSrc);
13994+
InsSrc = DAG.getBitcast(MVT::v2f64, InsSrc);
13995+
}
13996+
SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
13997+
ExtSrc.getValueType().getVectorElementType(),
13998+
ExtSrc, DAG.getVectorIdxConstant(ExtLane, dl));
13999+
SDValue Ins =
14000+
DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtSrc.getValueType(), InsSrc,
14001+
Ext, DAG.getVectorIdxConstant(InsLane, dl));
14002+
return DAG.getBitcast(VT, Ins);
14003+
};
14004+
auto BuildExtractInsert32 = [&DAG, &dl](SDValue ExtSrc, unsigned ExtLane,
14005+
SDValue InsSrc, unsigned InsLane) {
14006+
EVT VT = InsSrc.getValueType();
14007+
if (VT.getScalarSizeInBits() == 16) {
14008+
ExtSrc = DAG.getBitcast(MVT::v4f16, ExtSrc);
14009+
InsSrc = DAG.getBitcast(MVT::v4f16, InsSrc);
14010+
}
14011+
SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14012+
ExtSrc.getValueType().getVectorElementType(),
14013+
ExtSrc, DAG.getVectorIdxConstant(ExtLane, dl));
14014+
SDValue Ins =
14015+
DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtSrc.getValueType(), InsSrc,
14016+
Ext, DAG.getVectorIdxConstant(InsLane, dl));
14017+
return DAG.getBitcast(VT, Ins);
14018+
};
14019+
return generatePerfectShuffle<SDValue, MVT>(
14020+
PFTableIndex, V1, V2, PFEntry, V1, V2, BuildExtractInsert64,
14021+
BuildExtractInsert32, BuildRev, BuildDup, BuildExt, BuildZipLike);
1410114022
}
1410214023

1410314024
// Check for a "select shuffle", generating a BSL to pick between lanes in

0 commit comments

Comments
 (0)