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fix comments
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3 files changed

+28
-19
lines changed

3 files changed

+28
-19
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp‎

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -13,11 +13,7 @@
1313
#include "AMDGPU.h"
1414
#include "GCNSubtarget.h"
1515
#include "Utils/AMDGPUBaseInfo.h"
16-
<<<<<<< HEAD
17-
=======
1816
#include "llvm/Analysis/TargetTransformInfo.h"
19-
#include "llvm/CodeGen/TargetPassConfig.h"
20-
>>>>>>> 844ed4358374 ([AMDGPU][Attributor] Infer inreg attribute in `AMDGPUAttributor`)
2117
#include "llvm/IR/IntrinsicsAMDGPU.h"
2218
#include "llvm/IR/IntrinsicsR600.h"
2319
#include "llvm/Target/TargetMachine.h"
@@ -1359,19 +1355,21 @@ struct AAAMDGPUUniformArgument : public AAAMDGPUUniform {
13591355

13601356
ChangeStatus updateImpl(Attributor &A) override {
13611357
unsigned ArgNo = getAssociatedArgument()->getArgNo();
1362-
TargetMachine &TM =
1363-
static_cast<AMDGPUInformationCache &>(A.getInfoCache()).TM;
13641358

13651359
auto isUniform = [&](AbstractCallSite ACS) -> bool {
13661360
CallBase *CB = ACS.getInstruction();
13671361
Value *V = CB->getArgOperand(ArgNo);
1362+
if (isa<Constant>(V))
1363+
return true;
13681364
if (auto *Arg = dyn_cast<Argument>(V)) {
13691365
auto *AA = A.getOrCreateAAFor<AAAMDGPUUniform>(
13701366
IRPosition::argument(*Arg), this, DepClassTy::REQUIRED);
13711367
return AA && AA->isValidState();
13721368
}
1373-
TargetTransformInfo TTI = TM.getTargetTransformInfo(*CB->getFunction());
1374-
return TTI.isAlwaysUniform(V);
1369+
TargetTransformInfo *TTI =
1370+
A.getInfoCache().getAnalysisResultForFunction<TargetIRAnalysis>(
1371+
*CB->getFunction());
1372+
return TTI->isAlwaysUniform(V);
13751373
};
13761374

13771375
bool UsedAssumedInformation = true;

‎llvm/test/CodeGen/AMDGPU/aa-inreg-inference.ll‎

Lines changed: 20 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -4,21 +4,20 @@
44
@g1 = protected addrspace(1) externally_initialized global i32 0, align 4
55
@g2 = protected addrspace(1) externally_initialized global i32 0, align 4
66
@g3 = protected addrspace(1) externally_initialized global i32 0, align 4
7-
@g4 = protected addrspace(1) externally_initialized global i32 0, align 4
87

98
define internal void @callee_with_always_uniform_argument(ptr addrspace(1) %x, i32 %y) {
109
; CHECK-LABEL: define internal void @callee_with_always_uniform_argument(
1110
; CHECK-SAME: ptr addrspace(1) inreg [[X:%.*]], i32 inreg [[Y:%.*]]) #[[ATTR0:[0-9]+]] {
1211
; CHECK-NEXT: [[ENTRY:.*:]]
1312
; CHECK-NEXT: [[X_VAL:%.*]] = load i32, ptr addrspace(1) [[X]], align 4
14-
; CHECK-NEXT: store i32 [[X_VAL]], ptr addrspace(1) @g3, align 4
15-
; CHECK-NEXT: store i32 [[Y]], ptr addrspace(1) @g4, align 4
13+
; CHECK-NEXT: store i32 [[X_VAL]], ptr addrspace(1) @g2, align 4
14+
; CHECK-NEXT: store i32 [[Y]], ptr addrspace(1) @g3, align 4
1615
; CHECK-NEXT: ret void
1716
;
1817
entry:
1918
%x.val = load i32, ptr addrspace(1) %x, align 4
20-
store i32 %x.val, ptr addrspace(1) @g3, align 4
21-
store i32 %y, ptr addrspace(1) @g4, align 4
19+
store i32 %x.val, ptr addrspace(1) @g2, align 4
20+
store i32 %y, ptr addrspace(1) @g3, align 4
2221
ret void
2322
}
2423

@@ -36,19 +35,31 @@ entry:
3635
ret void
3736
}
3837

38+
define amdgpu_kernel void @kernel_with_constant(i32 %x) {
39+
; CHECK-LABEL: define amdgpu_kernel void @kernel_with_constant(
40+
; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] {
41+
; CHECK-NEXT: [[ENTRY:.*:]]
42+
; CHECK-NEXT: call void @callee_with_always_uniform_argument(ptr addrspace(1) @g1, i32 [[X]])
43+
; CHECK-NEXT: ret void
44+
;
45+
entry:
46+
call void @callee_with_always_uniform_argument(ptr addrspace(1) @g1, i32 %x)
47+
ret void
48+
}
49+
3950
define internal void @callee_without_always_uniform_argument(ptr addrspace(1) %x, i32 %y) {
4051
; CHECK-LABEL: define internal void @callee_without_always_uniform_argument(
4152
; CHECK-SAME: ptr addrspace(1) [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] {
4253
; CHECK-NEXT: [[ENTRY:.*:]]
4354
; CHECK-NEXT: [[X_VAL:%.*]] = load i32, ptr addrspace(1) [[X]], align 4
44-
; CHECK-NEXT: store i32 [[X_VAL]], ptr addrspace(1) @g3, align 4
45-
; CHECK-NEXT: store i32 [[Y]], ptr addrspace(1) @g4, align 4
55+
; CHECK-NEXT: store i32 [[X_VAL]], ptr addrspace(1) @g2, align 4
56+
; CHECK-NEXT: store i32 [[Y]], ptr addrspace(1) @g3, align 4
4657
; CHECK-NEXT: ret void
4758
;
4859
entry:
4960
%x.val = load i32, ptr addrspace(1) %x, align 4
50-
store i32 %x.val, ptr addrspace(1) @g3, align 4
51-
store i32 %y, ptr addrspace(1) @g4, align 4
61+
store i32 %x.val, ptr addrspace(1) @g2, align 4
62+
store i32 %y, ptr addrspace(1) @g3, align 4
5263
ret void
5364
}
5465

‎llvm/test/CodeGen/AMDGPU/attributor-noalias-addrspace.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -480,7 +480,7 @@ bb.2.end:
480480

481481
define internal void @callee_no_alias_addr_space_select(ptr %ptr1, ptr %ptr2, ptr %ptr3, i1 %cond1, i1 %cond2, i32 %val) #0 {
482482
; CHECK-LABEL: define internal void @callee_no_alias_addr_space_select(
483-
; CHECK-SAME: ptr [[PTR1:%.*]], ptr [[PTR2:%.*]], ptr [[PTR3:%.*]], i1 [[COND1:%.*]], i1 [[COND2:%.*]], i32 [[VAL:%.*]]) #[[ATTR1:[0-9]+]] {
483+
; CHECK-SAME: ptr [[PTR1:%.*]], ptr [[PTR2:%.*]], ptr [[PTR3:%.*]], i1 inreg [[COND1:%.*]], i1 inreg [[COND2:%.*]], i32 inreg [[VAL:%.*]]) #[[ATTR1:[0-9]+]] {
484484
; CHECK-NEXT: [[PTR4:%.*]] = select i1 [[COND1]], ptr addrspacecast (ptr addrspace(1) @gptr to ptr), ptr addrspacecast (ptr addrspace(4) @gptr2 to ptr)
485485
; CHECK-NEXT: [[PTR5:%.*]] = select i1 [[COND2]], ptr [[PTR4]], ptr addrspacecast (ptr addrspace(3) @gptr3 to ptr)
486486
; CHECK-NEXT: store i32 [[VAL]], ptr [[PTR5]], align 4, !noalias.addrspace [[META1:![0-9]+]]
@@ -516,7 +516,7 @@ define internal void @callee_no_alias_addr_space_select(ptr %ptr1, ptr %ptr2, pt
516516

517517
define internal void @callee_alias_addr_space_branch(ptr %ptr1, ptr %ptr2, ptr %ptr3, i1 %cond1, i1 %cond2, i32 %val) #0 {
518518
; CHECK-LABEL: define internal void @callee_alias_addr_space_branch(
519-
; CHECK-SAME: ptr [[PTR1:%.*]], ptr [[PTR2:%.*]], ptr [[PTR3:%.*]], i1 [[COND1:%.*]], i1 [[COND2:%.*]], i32 [[VAL:%.*]]) #[[ATTR1]] {
519+
; CHECK-SAME: ptr [[PTR1:%.*]], ptr [[PTR2:%.*]], ptr [[PTR3:%.*]], i1 inreg [[COND1:%.*]], i1 inreg [[COND2:%.*]], i32 inreg [[VAL:%.*]]) #[[ATTR1]] {
520520
; CHECK-NEXT: br i1 [[COND1]], label %[[BB_1_TRUE:.*]], label %[[BB_1_FALSE:.*]]
521521
; CHECK: [[BB_1_TRUE]]:
522522
; CHECK-NEXT: br label %[[BB_1_END:.*]]

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