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[AMDGPU][Attributor] Infer inreg attribute in AMDGPUAttributor
This patch introduces `AAAMDGPUUniformArgument` that can infer `inreg` function argument attribute. The idea is, for a function argument, if the corresponding call site arguments are always uniform, we can mark it as `inreg` thus pass it via SGPR. In addition, this AA is also able to propagate the inreg attribute if feasible.
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‎llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp‎

Lines changed: 119 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,11 @@
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#include "AMDGPU.h"
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#include "GCNSubtarget.h"
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#include "Utils/AMDGPUBaseInfo.h"
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<<<<<<< HEAD
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=======
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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>>>>>>> 844ed4358374 ([AMDGPU][Attributor] Infer inreg attribute in `AMDGPUAttributor`)
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#include "llvm/IR/IntrinsicsAMDGPU.h"
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#include "llvm/IR/IntrinsicsR600.h"
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#include "llvm/Target/TargetMachine.h"
@@ -1296,6 +1301,114 @@ struct AAAMDGPUNoAGPR
12961301

12971302
const char AAAMDGPUNoAGPR::ID = 0;
12981303

1304+
struct AAAMDGPUUniform : public StateWrapper<BooleanState, AbstractAttribute> {
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using Base = StateWrapper<BooleanState, AbstractAttribute>;
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AAAMDGPUUniform(const IRPosition &IRP, Attributor &A) : Base(IRP) {}
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/// Create an abstract attribute view for the position \p IRP.
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static AAAMDGPUUniform &createForPosition(const IRPosition &IRP,
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Attributor &A);
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/// See AbstractAttribute::getName()
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StringRef getName() const override { return "AAAMDGPUUniform"; }
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const std::string getAsStr(Attributor *A) const override {
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return getAssumed() ? "uniform" : "divergent";
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}
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void trackStatistics() const override {}
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/// See AbstractAttribute::getIdAddr()
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const char *getIdAddr() const override { return &ID; }
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/// This function should return true if the type of the \p AA is
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/// AAAMDGPUUniform
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static bool classof(const AbstractAttribute *AA) {
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return (AA->getIdAddr() == &ID);
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}
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/// Unique ID (due to the unique address)
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static const char ID;
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};
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const char AAAMDGPUUniform::ID = 0;
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/// This AA is to infer the inreg attribute for a function argument.
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struct AAAMDGPUUniformArgument : public AAAMDGPUUniform {
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AAAMDGPUUniformArgument(const IRPosition &IRP, Attributor &A)
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: AAAMDGPUUniform(IRP, A) {}
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void initialize(Attributor &A) override {
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Argument *Arg = getAssociatedArgument();
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CallingConv::ID CC = Arg->getParent()->getCallingConv();
1344+
if (Arg->hasAttribute(Attribute::InReg)) {
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indicateOptimisticFixpoint();
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return;
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}
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if (AMDGPU::isEntryFunctionCC(CC)) {
1350+
// We only use isArgPassedInSGPR on kernel entry function argument, so
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// even if we will use SPGR for non-uniform i1 argument passing, it will
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// not affect this.
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if (AMDGPU::isArgPassedInSGPR(Arg))
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indicateOptimisticFixpoint();
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else
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indicatePessimisticFixpoint();
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}
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}
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ChangeStatus updateImpl(Attributor &A) override {
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unsigned ArgNo = getAssociatedArgument()->getArgNo();
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TargetMachine &TM =
1363+
static_cast<AMDGPUInformationCache &>(A.getInfoCache()).TM;
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auto isUniform = [&](AbstractCallSite ACS) -> bool {
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CallBase *CB = ACS.getInstruction();
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Value *V = CB->getArgOperand(ArgNo);
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if (auto *Arg = dyn_cast<Argument>(V)) {
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auto *AA = A.getOrCreateAAFor<AAAMDGPUUniform>(
1370+
IRPosition::argument(*Arg), this, DepClassTy::REQUIRED);
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return AA && AA->isValidState();
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}
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TargetTransformInfo TTI = TM.getTargetTransformInfo(*CB->getFunction());
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return TTI.isAlwaysUniform(V);
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};
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bool UsedAssumedInformation = true;
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if (!A.checkForAllCallSites(isUniform, *this, /*RequireAllCallSites=*/true,
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UsedAssumedInformation))
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return indicatePessimisticFixpoint();
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if (!UsedAssumedInformation)
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return indicateOptimisticFixpoint();
1384+
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return ChangeStatus::UNCHANGED;
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}
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ChangeStatus manifest(Attributor &A) override {
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Argument *Arg = getAssociatedArgument();
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// If the argument already has inreg attribute, we will not do anything
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// about it.
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if (Arg->hasAttribute(Attribute::InReg))
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return ChangeStatus::UNCHANGED;
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if (AMDGPU::isEntryFunctionCC(Arg->getParent()->getCallingConv()))
1395+
return ChangeStatus::UNCHANGED;
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LLVMContext &Ctx = Arg->getContext();
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return A.manifestAttrs(getIRPosition(),
1398+
{Attribute::get(Ctx, Attribute::InReg)});
1399+
}
1400+
};
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1402+
AAAMDGPUUniform &AAAMDGPUUniform::createForPosition(const IRPosition &IRP,
1403+
Attributor &A) {
1404+
switch (IRP.getPositionKind()) {
1405+
case IRPosition::IRP_ARGUMENT:
1406+
return *new (A.Allocator) AAAMDGPUUniformArgument(IRP, A);
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default:
1408+
llvm_unreachable("not a valid position for AAAMDGPUUniform");
1409+
}
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}
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12991412
/// Performs the final check and updates the 'amdgpu-waves-per-eu' attribute
13001413
/// based on the finalized 'amdgpu-flat-work-group-size' attribute.
13011414
/// Both attributes start with narrow ranges that expand during iteration.
@@ -1382,7 +1495,7 @@ static bool runImpl(Module &M, AnalysisGetter &AG, TargetMachine &TM,
13821495
&AAAMDMaxNumWorkgroups::ID, &AAAMDWavesPerEU::ID, &AAAMDGPUNoAGPR::ID,
13831496
&AACallEdges::ID, &AAPointerInfo::ID, &AAPotentialConstantValues::ID,
13841497
&AAUnderlyingObjects::ID, &AANoAliasAddrSpace::ID, &AAAddressSpace::ID,
1385-
&AAIndirectCallInfo::ID});
1498+
&AAIndirectCallInfo::ID, &AAAMDGPUUniform::ID});
13861499

13871500
AttributorConfig AC(CGUpdater);
13881501
AC.IsClosedWorldModule = Options.IsClosedWorld;
@@ -1435,6 +1548,11 @@ static bool runImpl(Module &M, AnalysisGetter &AG, TargetMachine &TM,
14351548
A.getOrCreateAAFor<AAAddressSpace>(IRPosition::value(*Ptr));
14361549
A.getOrCreateAAFor<AANoAliasAddrSpace>(IRPosition::value(*Ptr));
14371550
}
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1552+
if (!AMDGPU::isEntryFunctionCC(F->getCallingConv())) {
1553+
for (auto &Arg : F->args())
1554+
A.getOrCreateAAFor<AAAMDGPUUniform>(IRPosition::argument(Arg));
1555+
}
14381556
}
14391557
}
14401558

‎llvm/test/CodeGen/AMDGPU/aa-inreg-inference.ll‎

Lines changed: 74 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,74 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-attributor %s -o - | FileCheck %s
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@g1 = protected addrspace(1) externally_initialized global i32 0, align 4
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@g2 = protected addrspace(1) externally_initialized global i32 0, align 4
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@g3 = protected addrspace(1) externally_initialized global i32 0, align 4
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@g4 = protected addrspace(1) externally_initialized global i32 0, align 4
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9+
define internal void @callee_with_always_uniform_argument(ptr addrspace(1) %x, i32 %y) {
10+
; CHECK-LABEL: define internal void @callee_with_always_uniform_argument(
11+
; CHECK-SAME: ptr addrspace(1) inreg [[X:%.*]], i32 inreg [[Y:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[X_VAL:%.*]] = load i32, ptr addrspace(1) [[X]], align 4
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; CHECK-NEXT: store i32 [[X_VAL]], ptr addrspace(1) @g3, align 4
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; CHECK-NEXT: store i32 [[Y]], ptr addrspace(1) @g4, align 4
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; CHECK-NEXT: ret void
17+
;
18+
entry:
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%x.val = load i32, ptr addrspace(1) %x, align 4
20+
store i32 %x.val, ptr addrspace(1) @g3, align 4
21+
store i32 %y, ptr addrspace(1) @g4, align 4
22+
ret void
23+
}
24+
25+
define amdgpu_kernel void @kernel_with_readfirstlane(ptr addrspace(1) %p, i32 %x) {
26+
; CHECK-LABEL: define amdgpu_kernel void @kernel_with_readfirstlane(
27+
; CHECK-SAME: ptr addrspace(1) [[P:%.*]], i32 [[X:%.*]]) #[[ATTR0]] {
28+
; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[P0:%.*]] = call ptr addrspace(1) @llvm.amdgcn.readfirstlane.p1(ptr addrspace(1) [[P]])
30+
; CHECK-NEXT: call void @callee_with_always_uniform_argument(ptr addrspace(1) [[P0]], i32 [[X]])
31+
; CHECK-NEXT: ret void
32+
;
33+
entry:
34+
%p0 = call ptr addrspace(1) @llvm.amdgcn.readfirstlane.p1(ptr addrspace(1) %p)
35+
call void @callee_with_always_uniform_argument(ptr addrspace(1) %p0, i32 %x)
36+
ret void
37+
}
38+
39+
define internal void @callee_without_always_uniform_argument(ptr addrspace(1) %x, i32 %y) {
40+
; CHECK-LABEL: define internal void @callee_without_always_uniform_argument(
41+
; CHECK-SAME: ptr addrspace(1) [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] {
42+
; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[X_VAL:%.*]] = load i32, ptr addrspace(1) [[X]], align 4
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; CHECK-NEXT: store i32 [[X_VAL]], ptr addrspace(1) @g3, align 4
45+
; CHECK-NEXT: store i32 [[Y]], ptr addrspace(1) @g4, align 4
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; CHECK-NEXT: ret void
47+
;
48+
entry:
49+
%x.val = load i32, ptr addrspace(1) %x, align 4
50+
store i32 %x.val, ptr addrspace(1) @g3, align 4
51+
store i32 %y, ptr addrspace(1) @g4, align 4
52+
ret void
53+
}
54+
55+
define amdgpu_kernel void @kernel_with_divergent_callsite_argument(ptr addrspace(1) %p, i32 %x) {
56+
; CHECK-LABEL: define amdgpu_kernel void @kernel_with_divergent_callsite_argument(
57+
; CHECK-SAME: ptr addrspace(1) [[P:%.*]], i32 [[X:%.*]]) #[[ATTR0]] {
58+
; CHECK-NEXT: [[ENTRY:.*:]]
59+
; CHECK-NEXT: [[ID_X:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
60+
; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr addrspace(1) [[P]], i32 [[ID_X]]
61+
; CHECK-NEXT: [[D:%.*]] = load i32, ptr addrspace(1) [[GEP]], align 4
62+
; CHECK-NEXT: call void @callee_without_always_uniform_argument(ptr addrspace(1) [[GEP]], i32 [[D]])
63+
; CHECK-NEXT: ret void
64+
;
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entry:
66+
%id.x = call i32 @llvm.amdgcn.workitem.id.x()
67+
%gep = getelementptr i32, ptr addrspace(1) %p, i32 %id.x
68+
%d = load i32, ptr addrspace(1) %gep
69+
call void @callee_without_always_uniform_argument(ptr addrspace(1) %gep, i32 %d)
70+
ret void
71+
}
72+
73+
declare ptr addrspace(1) @llvm.amdgcn.readfirstlane.p1(ptr addrspace(1))
74+
declare noundef i32 @llvm.amdgcn.workitem.id.x()

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