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1 parent d8c9d58 commit 321de07Copy full SHA for 321de07
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -13201,9 +13201,7 @@ SDValue DAGCombiner::matchVSelectOpSizesWithSetCC(SDNode *Cast) {
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unsigned CastOpcode = Cast->getOpcode();
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assert((CastOpcode == ISD::SIGN_EXTEND || CastOpcode == ISD::ZERO_EXTEND ||
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CastOpcode == ISD::TRUNCATE || CastOpcode == ISD::FP_EXTEND ||
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- CastOpcode == ISD::TRUNCATE_SSAT_S ||
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- CastOpcode == ISD::TRUNCATE_SSAT_U ||
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- CastOpcode == ISD::TRUNCATE_USAT_U || CastOpcode == ISD::FP_ROUND) &&
+ CastOpcode == ISD::FP_ROUND) &&
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"Unexpected opcode for vector select narrowing/widening");
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// We only do this transform before legal ops because the pattern may be
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