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[RISCV] Don't support TRUNCATE_SSAT_U. (#104468)
RISC-V doesn't have an instruction for this. We were treating it the same as TRUNCATE_USAT_U.
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5 files changed

+136
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‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 7 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -784,9 +784,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
784784

785785
// Integer VTs are lowered as a series of "RISCVISD::TRUNCATE_VECTOR_VL"
786786
// nodes which truncate by one power of two at a time.
787-
setOperationAction({ISD::TRUNCATE, ISD::TRUNCATE_SSAT_S,
788-
ISD::TRUNCATE_SSAT_U, ISD::TRUNCATE_USAT_U},
789-
VT, Custom);
787+
setOperationAction(
788+
{ISD::TRUNCATE, ISD::TRUNCATE_SSAT_S, ISD::TRUNCATE_USAT_U}, VT,
789+
Custom);
790790

791791
// Custom-lower insert/extract operations to simplify patterns.
792792
setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT}, VT,
@@ -1102,9 +1102,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
11021102

11031103
setOperationAction(ISD::SELECT, VT, Custom);
11041104

1105-
setOperationAction({ISD::TRUNCATE, ISD::TRUNCATE_SSAT_S,
1106-
ISD::TRUNCATE_SSAT_U, ISD::TRUNCATE_USAT_U},
1107-
VT, Custom);
1105+
setOperationAction(
1106+
{ISD::TRUNCATE, ISD::TRUNCATE_SSAT_S, ISD::TRUNCATE_USAT_U}, VT,
1107+
Custom);
11081108

11091109
setOperationAction(ISD::BITCAST, VT, Custom);
11101110

@@ -6232,7 +6232,6 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
62326232
}
62336233
case ISD::TRUNCATE:
62346234
case ISD::TRUNCATE_SSAT_S:
6235-
case ISD::TRUNCATE_SSAT_U:
62366235
case ISD::TRUNCATE_USAT_U:
62376236
// Only custom-lower vector truncates
62386237
if (!Op.getSimpleValueType().isVector())
@@ -8119,7 +8118,7 @@ SDValue RISCVTargetLowering::lowerVectorTruncLike(SDValue Op,
81198118
unsigned NewOpc;
81208119
if (Opc == ISD::TRUNCATE_SSAT_S)
81218120
NewOpc = RISCVISD::TRUNCATE_VECTOR_VL_SSAT;
8122-
else if (Opc == ISD::TRUNCATE_SSAT_U || Opc == ISD::TRUNCATE_USAT_U)
8121+
else if (Opc == ISD::TRUNCATE_USAT_U)
81238122
NewOpc = RISCVISD::TRUNCATE_VECTOR_VL_USAT;
81248123
else
81258124
NewOpc = RISCVISD::TRUNCATE_VECTOR_VL;

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-sat-clip.ll‎

Lines changed: 24 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -101,8 +101,10 @@ define void @trunc_sat_u8u16_notopt(ptr %x, ptr %y) {
101101
define void @trunc_sat_u8u16_maxmin(ptr %x, ptr %y) {
102102
; CHECK-LABEL: trunc_sat_u8u16_maxmin:
103103
; CHECK: # %bb.0:
104-
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
104+
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
105105
; CHECK-NEXT: vle16.v v8, (a0)
106+
; CHECK-NEXT: vmax.vx v8, v8, zero
107+
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
106108
; CHECK-NEXT: vnclipu.wi v8, v8, 0
107109
; CHECK-NEXT: vse8.v v8, (a1)
108110
; CHECK-NEXT: ret
@@ -117,8 +119,10 @@ define void @trunc_sat_u8u16_maxmin(ptr %x, ptr %y) {
117119
define void @trunc_sat_u8u16_minmax(ptr %x, ptr %y) {
118120
; CHECK-LABEL: trunc_sat_u8u16_minmax:
119121
; CHECK: # %bb.0:
120-
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
122+
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
121123
; CHECK-NEXT: vle16.v v8, (a0)
124+
; CHECK-NEXT: vmax.vx v8, v8, zero
125+
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
122126
; CHECK-NEXT: vnclipu.wi v8, v8, 0
123127
; CHECK-NEXT: vse8.v v8, (a1)
124128
; CHECK-NEXT: ret
@@ -352,8 +356,10 @@ define void @trunc_sat_u32u64_min(ptr %x, ptr %y) {
352356
define void @trunc_sat_u32u64_maxmin(ptr %x, ptr %y) {
353357
; CHECK-LABEL: trunc_sat_u32u64_maxmin:
354358
; CHECK: # %bb.0:
355-
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
359+
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
356360
; CHECK-NEXT: vle64.v v8, (a0)
361+
; CHECK-NEXT: vmax.vx v8, v8, zero
362+
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
357363
; CHECK-NEXT: vnclipu.wi v10, v8, 0
358364
; CHECK-NEXT: vse32.v v10, (a1)
359365
; CHECK-NEXT: ret
@@ -368,8 +374,10 @@ define void @trunc_sat_u32u64_maxmin(ptr %x, ptr %y) {
368374
define void @trunc_sat_u32u64_minmax(ptr %x, ptr %y) {
369375
; CHECK-LABEL: trunc_sat_u32u64_minmax:
370376
; CHECK: # %bb.0:
371-
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
377+
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
372378
; CHECK-NEXT: vle64.v v8, (a0)
379+
; CHECK-NEXT: vmax.vx v8, v8, zero
380+
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
373381
; CHECK-NEXT: vnclipu.wi v10, v8, 0
374382
; CHECK-NEXT: vse32.v v10, (a1)
375383
; CHECK-NEXT: ret
@@ -437,8 +445,10 @@ define void @trunc_sat_u8u32_min(ptr %x, ptr %y) {
437445
define void @trunc_sat_u8u32_maxmin(ptr %x, ptr %y) {
438446
; CHECK-LABEL: trunc_sat_u8u32_maxmin:
439447
; CHECK: # %bb.0:
440-
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
448+
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
441449
; CHECK-NEXT: vle32.v v8, (a0)
450+
; CHECK-NEXT: vmax.vx v8, v8, zero
451+
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
442452
; CHECK-NEXT: vnclipu.wi v8, v8, 0
443453
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
444454
; CHECK-NEXT: vnclipu.wi v8, v8, 0
@@ -455,8 +465,10 @@ define void @trunc_sat_u8u32_maxmin(ptr %x, ptr %y) {
455465
define void @trunc_sat_u8u32_minmax(ptr %x, ptr %y) {
456466
; CHECK-LABEL: trunc_sat_u8u32_minmax:
457467
; CHECK: # %bb.0:
458-
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
468+
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
459469
; CHECK-NEXT: vle32.v v8, (a0)
470+
; CHECK-NEXT: vmax.vx v8, v8, zero
471+
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
460472
; CHECK-NEXT: vnclipu.wi v8, v8, 0
461473
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
462474
; CHECK-NEXT: vnclipu.wi v8, v8, 0
@@ -532,8 +544,10 @@ define void @trunc_sat_u8u64_min(ptr %x, ptr %y) {
532544
define void @trunc_sat_u8u64_maxmin(ptr %x, ptr %y) {
533545
; CHECK-LABEL: trunc_sat_u8u64_maxmin:
534546
; CHECK: # %bb.0:
535-
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
547+
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
536548
; CHECK-NEXT: vle64.v v8, (a0)
549+
; CHECK-NEXT: vmax.vx v8, v8, zero
550+
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
537551
; CHECK-NEXT: vnclipu.wi v10, v8, 0
538552
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
539553
; CHECK-NEXT: vnclipu.wi v8, v10, 0
@@ -552,8 +566,10 @@ define void @trunc_sat_u8u64_maxmin(ptr %x, ptr %y) {
552566
define void @trunc_sat_u8u64_minmax(ptr %x, ptr %y) {
553567
; CHECK-LABEL: trunc_sat_u8u64_minmax:
554568
; CHECK: # %bb.0:
555-
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
569+
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
556570
; CHECK-NEXT: vle64.v v8, (a0)
571+
; CHECK-NEXT: vmax.vx v8, v8, zero
572+
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
557573
; CHECK-NEXT: vnclipu.wi v10, v8, 0
558574
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
559575
; CHECK-NEXT: vnclipu.wi v8, v10, 0

‎llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll‎

Lines changed: 42 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -113,6 +113,7 @@ define <2 x i32> @ustest_f64i32(<2 x double> %x) {
113113
; CHECK-V: # %bb.0: # %entry
114114
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
115115
; CHECK-V-NEXT: vfcvt.rtz.x.f.v v8, v8
116+
; CHECK-V-NEXT: vmax.vx v8, v8, zero
116117
; CHECK-V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
117118
; CHECK-V-NEXT: vnclipu.wi v8, v8, 0
118119
; CHECK-V-NEXT: ret
@@ -303,6 +304,9 @@ define <4 x i32> @ustest_f32i32(<4 x float> %x) {
303304
; CHECK-V: # %bb.0: # %entry
304305
; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
305306
; CHECK-V-NEXT: vfwcvt.rtz.x.f.v v10, v8
307+
; CHECK-V-NEXT: vsetvli zero, zero, e64, m2, ta, ma
308+
; CHECK-V-NEXT: vmax.vx v10, v10, zero
309+
; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
306310
; CHECK-V-NEXT: vnclipu.wi v8, v10, 0
307311
; CHECK-V-NEXT: ret
308312
entry:
@@ -797,16 +801,17 @@ define <4 x i32> @ustest_f16i32(<4 x half> %x) {
797801
; CHECK-V-NEXT: call __extendhfsf2
798802
; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz
799803
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
800-
; CHECK-V-NEXT: vmv.s.x v10, a0
804+
; CHECK-V-NEXT: vmv.s.x v8, a0
801805
; CHECK-V-NEXT: addi a0, sp, 16
802-
; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
803-
; CHECK-V-NEXT: vslideup.vi v10, v8, 1
806+
; CHECK-V-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload
807+
; CHECK-V-NEXT: vslideup.vi v8, v9, 1
804808
; CHECK-V-NEXT: csrr a0, vlenb
805809
; CHECK-V-NEXT: add a0, sp, a0
806810
; CHECK-V-NEXT: addi a0, a0, 16
807-
; CHECK-V-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload
811+
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
808812
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
809-
; CHECK-V-NEXT: vslideup.vi v10, v8, 2
813+
; CHECK-V-NEXT: vslideup.vi v8, v10, 2
814+
; CHECK-V-NEXT: vmax.vx v10, v8, zero
810815
; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
811816
; CHECK-V-NEXT: vnclipu.wi v8, v10, 0
812817
; CHECK-V-NEXT: csrr a0, vlenb
@@ -939,8 +944,9 @@ define <2 x i16> @ustest_f64i16(<2 x double> %x) {
939944
; CHECK-V: # %bb.0: # %entry
940945
; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
941946
; CHECK-V-NEXT: vfncvt.rtz.x.f.w v9, v8
947+
; CHECK-V-NEXT: vmax.vx v8, v9, zero
942948
; CHECK-V-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
943-
; CHECK-V-NEXT: vnclipu.wi v8, v9, 0
949+
; CHECK-V-NEXT: vnclipu.wi v8, v8, 0
944950
; CHECK-V-NEXT: ret
945951
entry:
946952
%conv = fptosi <2 x double> %x to <2 x i32>
@@ -1133,6 +1139,7 @@ define <4 x i16> @ustest_f32i16(<4 x float> %x) {
11331139
; CHECK-V: # %bb.0: # %entry
11341140
; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
11351141
; CHECK-V-NEXT: vfcvt.rtz.x.f.v v8, v8
1142+
; CHECK-V-NEXT: vmax.vx v8, v8, zero
11361143
; CHECK-V-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
11371144
; CHECK-V-NEXT: vnclipu.wi v8, v8, 0
11381145
; CHECK-V-NEXT: ret
@@ -2107,23 +2114,24 @@ define <8 x i16> @ustest_f16i16(<8 x half> %x) {
21072114
; CHECK-V-NEXT: call __extendhfsf2
21082115
; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz
21092116
; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
2110-
; CHECK-V-NEXT: vmv.s.x v10, a0
2117+
; CHECK-V-NEXT: vmv.s.x v8, a0
21112118
; CHECK-V-NEXT: addi a0, sp, 16
2112-
; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
2113-
; CHECK-V-NEXT: vslideup.vi v10, v8, 1
2119+
; CHECK-V-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload
2120+
; CHECK-V-NEXT: vslideup.vi v8, v9, 1
21142121
; CHECK-V-NEXT: csrr a0, vlenb
21152122
; CHECK-V-NEXT: add a0, sp, a0
21162123
; CHECK-V-NEXT: addi a0, a0, 16
2117-
; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
2124+
; CHECK-V-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload
21182125
; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
2119-
; CHECK-V-NEXT: vslideup.vi v10, v8, 2
2126+
; CHECK-V-NEXT: vslideup.vi v8, v9, 2
21202127
; CHECK-V-NEXT: csrr a0, vlenb
21212128
; CHECK-V-NEXT: slli a0, a0, 1
21222129
; CHECK-V-NEXT: add a0, sp, a0
21232130
; CHECK-V-NEXT: addi a0, a0, 16
2124-
; CHECK-V-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload
2131+
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
21252132
; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
2126-
; CHECK-V-NEXT: vslideup.vi v10, v8, 4
2133+
; CHECK-V-NEXT: vslideup.vi v8, v10, 4
2134+
; CHECK-V-NEXT: vmax.vx v10, v8, zero
21272135
; CHECK-V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
21282136
; CHECK-V-NEXT: vnclipu.wi v8, v10, 0
21292137
; CHECK-V-NEXT: csrr a0, vlenb
@@ -3465,6 +3473,7 @@ define <2 x i32> @ustest_f64i32_mm(<2 x double> %x) {
34653473
; CHECK-V: # %bb.0: # %entry
34663474
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
34673475
; CHECK-V-NEXT: vfcvt.rtz.x.f.v v8, v8
3476+
; CHECK-V-NEXT: vmax.vx v8, v8, zero
34683477
; CHECK-V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
34693478
; CHECK-V-NEXT: vnclipu.wi v8, v8, 0
34703479
; CHECK-V-NEXT: ret
@@ -3650,6 +3659,9 @@ define <4 x i32> @ustest_f32i32_mm(<4 x float> %x) {
36503659
; CHECK-V: # %bb.0: # %entry
36513660
; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
36523661
; CHECK-V-NEXT: vfwcvt.rtz.x.f.v v10, v8
3662+
; CHECK-V-NEXT: vsetvli zero, zero, e64, m2, ta, ma
3663+
; CHECK-V-NEXT: vmax.vx v10, v10, zero
3664+
; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
36533665
; CHECK-V-NEXT: vnclipu.wi v8, v10, 0
36543666
; CHECK-V-NEXT: ret
36553667
entry:
@@ -4139,16 +4151,17 @@ define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) {
41394151
; CHECK-V-NEXT: call __extendhfsf2
41404152
; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz
41414153
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
4142-
; CHECK-V-NEXT: vmv.s.x v10, a0
4154+
; CHECK-V-NEXT: vmv.s.x v8, a0
41434155
; CHECK-V-NEXT: addi a0, sp, 16
4144-
; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
4145-
; CHECK-V-NEXT: vslideup.vi v10, v8, 1
4156+
; CHECK-V-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload
4157+
; CHECK-V-NEXT: vslideup.vi v8, v9, 1
41464158
; CHECK-V-NEXT: csrr a0, vlenb
41474159
; CHECK-V-NEXT: add a0, sp, a0
41484160
; CHECK-V-NEXT: addi a0, a0, 16
4149-
; CHECK-V-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload
4161+
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
41504162
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
4151-
; CHECK-V-NEXT: vslideup.vi v10, v8, 2
4163+
; CHECK-V-NEXT: vslideup.vi v8, v10, 2
4164+
; CHECK-V-NEXT: vmax.vx v10, v8, zero
41524165
; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
41534166
; CHECK-V-NEXT: vnclipu.wi v8, v10, 0
41544167
; CHECK-V-NEXT: csrr a0, vlenb
@@ -4276,8 +4289,9 @@ define <2 x i16> @ustest_f64i16_mm(<2 x double> %x) {
42764289
; CHECK-V: # %bb.0: # %entry
42774290
; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
42784291
; CHECK-V-NEXT: vfncvt.rtz.x.f.w v9, v8
4292+
; CHECK-V-NEXT: vmax.vx v8, v9, zero
42794293
; CHECK-V-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
4280-
; CHECK-V-NEXT: vnclipu.wi v8, v9, 0
4294+
; CHECK-V-NEXT: vnclipu.wi v8, v8, 0
42814295
; CHECK-V-NEXT: ret
42824296
entry:
42834297
%conv = fptosi <2 x double> %x to <2 x i32>
@@ -4465,6 +4479,7 @@ define <4 x i16> @ustest_f32i16_mm(<4 x float> %x) {
44654479
; CHECK-V: # %bb.0: # %entry
44664480
; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
44674481
; CHECK-V-NEXT: vfcvt.rtz.x.f.v v8, v8
4482+
; CHECK-V-NEXT: vmax.vx v8, v8, zero
44684483
; CHECK-V-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
44694484
; CHECK-V-NEXT: vnclipu.wi v8, v8, 0
44704485
; CHECK-V-NEXT: ret
@@ -5434,23 +5449,24 @@ define <8 x i16> @ustest_f16i16_mm(<8 x half> %x) {
54345449
; CHECK-V-NEXT: call __extendhfsf2
54355450
; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz
54365451
; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
5437-
; CHECK-V-NEXT: vmv.s.x v10, a0
5452+
; CHECK-V-NEXT: vmv.s.x v8, a0
54385453
; CHECK-V-NEXT: addi a0, sp, 16
5439-
; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
5440-
; CHECK-V-NEXT: vslideup.vi v10, v8, 1
5454+
; CHECK-V-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload
5455+
; CHECK-V-NEXT: vslideup.vi v8, v9, 1
54415456
; CHECK-V-NEXT: csrr a0, vlenb
54425457
; CHECK-V-NEXT: add a0, sp, a0
54435458
; CHECK-V-NEXT: addi a0, a0, 16
5444-
; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
5459+
; CHECK-V-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload
54455460
; CHECK-V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
5446-
; CHECK-V-NEXT: vslideup.vi v10, v8, 2
5461+
; CHECK-V-NEXT: vslideup.vi v8, v9, 2
54475462
; CHECK-V-NEXT: csrr a0, vlenb
54485463
; CHECK-V-NEXT: slli a0, a0, 1
54495464
; CHECK-V-NEXT: add a0, sp, a0
54505465
; CHECK-V-NEXT: addi a0, a0, 16
5451-
; CHECK-V-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload
5466+
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
54525467
; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
5453-
; CHECK-V-NEXT: vslideup.vi v10, v8, 4
5468+
; CHECK-V-NEXT: vslideup.vi v8, v10, 4
5469+
; CHECK-V-NEXT: vmax.vx v10, v8, zero
54545470
; CHECK-V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
54555471
; CHECK-V-NEXT: vnclipu.wi v8, v10, 0
54565472
; CHECK-V-NEXT: csrr a0, vlenb

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