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[VE] Use MCRegister instead of unsigned. NFC (#167460)
1 parent cc184e3 commit 321afc7

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+39
-37
lines changed

1 file changed

+39
-37
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‎llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp‎

Lines changed: 39 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ class VEAsmParser : public MCTargetAsmParser {
5454
uint64_t &ErrorInfo,
5555
bool MatchingInlineAsm) override;
5656
bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
57-
int parseRegisterName(MCRegister (*matchFn)(StringRef));
57+
MCRegister parseRegisterName(MCRegister (*matchFn)(StringRef));
5858
ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
5959
SMLoc &EndLoc) override;
6060
bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
@@ -169,16 +169,16 @@ class VEOperand : public MCParsedAsmOperand {
169169
};
170170

171171
struct RegOp {
172-
unsigned RegNum;
172+
MCRegister Reg;
173173
};
174174

175175
struct ImmOp {
176176
const MCExpr *Val;
177177
};
178178

179179
struct MemOp {
180-
unsigned Base;
181-
unsigned IndexReg;
180+
MCRegister Base;
181+
MCRegister IndexReg;
182182
const MCExpr *Index;
183183
const MCExpr *Offset;
184184
};
@@ -342,22 +342,22 @@ class VEOperand : public MCParsedAsmOperand {
342342

343343
MCRegister getReg() const override {
344344
assert((Kind == k_Register) && "Invalid access!");
345-
return Reg.RegNum;
345+
return Reg.Reg;
346346
}
347347

348348
const MCExpr *getImm() const {
349349
assert((Kind == k_Immediate) && "Invalid access!");
350350
return Imm.Val;
351351
}
352352

353-
unsigned getMemBase() const {
353+
MCRegister getMemBase() const {
354354
assert((Kind == k_MemoryRegRegImm || Kind == k_MemoryRegImmImm ||
355355
Kind == k_MemoryRegImm) &&
356356
"Invalid access!");
357357
return Mem.Base;
358358
}
359359

360-
unsigned getMemIndexReg() const {
360+
MCRegister getMemIndexReg() const {
361361
assert((Kind == k_MemoryRegRegImm || Kind == k_MemoryZeroRegImm) &&
362362
"Invalid access!");
363363
return Mem.IndexReg;
@@ -415,28 +415,29 @@ class VEOperand : public MCParsedAsmOperand {
415415
OS << "Token: " << getToken() << "\n";
416416
break;
417417
case k_Register:
418-
OS << "Reg: #" << getReg() << "\n";
418+
OS << "Reg: #" << getReg().id() << "\n";
419419
break;
420420
case k_Immediate:
421421
OS << "Imm: " << getImm() << "\n";
422422
break;
423423
case k_MemoryRegRegImm:
424424
assert(getMemOffset() != nullptr);
425-
OS << "Mem: #" << getMemBase() << "+#" << getMemIndexReg() << "+";
425+
OS << "Mem: #" << getMemBase().id() << "+#" << getMemIndexReg().id()
426+
<< "+";
426427
MAI.printExpr(OS, *getMemOffset());
427428
OS << "\n";
428429
break;
429430
case k_MemoryRegImmImm:
430431
assert(getMemIndex() != nullptr && getMemOffset() != nullptr);
431-
OS << "Mem: #" << getMemBase() << "+";
432+
OS << "Mem: #" << getMemBase().id() << "+";
432433
MAI.printExpr(OS, *getMemIndex());
433434
OS << "+";
434435
MAI.printExpr(OS, *getMemOffset());
435436
OS << "\n";
436437
break;
437438
case k_MemoryZeroRegImm:
438439
assert(getMemOffset() != nullptr);
439-
OS << "Mem: 0+#" << getMemIndexReg() << "+";
440+
OS << "Mem: 0+#" << getMemIndexReg().id() << "+";
440441
MAI.printExpr(OS, *getMemOffset());
441442
OS << "\n";
442443
break;
@@ -450,7 +451,7 @@ class VEOperand : public MCParsedAsmOperand {
450451
break;
451452
case k_MemoryRegImm:
452453
assert(getMemOffset() != nullptr);
453-
OS << "Mem: #" << getMemBase() << "+";
454+
OS << "Mem: #" << getMemBase().id() << "+";
454455
MAI.printExpr(OS, *getMemOffset());
455456
OS << "\n";
456457
break;
@@ -606,10 +607,10 @@ class VEOperand : public MCParsedAsmOperand {
606607
return Op;
607608
}
608609

609-
static std::unique_ptr<VEOperand> CreateReg(unsigned RegNum, SMLoc S,
610+
static std::unique_ptr<VEOperand> CreateReg(MCRegister Reg, SMLoc S,
610611
SMLoc E) {
611612
auto Op = std::make_unique<VEOperand>(k_Register);
612-
Op->Reg.RegNum = RegNum;
613+
Op->Reg.Reg = Reg;
613614
Op->StartLoc = S;
614615
Op->EndLoc = E;
615616
return Op;
@@ -653,38 +654,38 @@ class VEOperand : public MCParsedAsmOperand {
653654
}
654655

655656
static bool MorphToI32Reg(VEOperand &Op) {
656-
unsigned Reg = Op.getReg();
657+
MCRegister Reg = Op.getReg();
657658
unsigned regIdx = Reg - VE::SX0;
658659
if (regIdx > 63)
659660
return false;
660-
Op.Reg.RegNum = I32Regs[regIdx];
661+
Op.Reg.Reg = I32Regs[regIdx];
661662
return true;
662663
}
663664

664665
static bool MorphToF32Reg(VEOperand &Op) {
665-
unsigned Reg = Op.getReg();
666+
MCRegister Reg = Op.getReg();
666667
unsigned regIdx = Reg - VE::SX0;
667668
if (regIdx > 63)
668669
return false;
669-
Op.Reg.RegNum = F32Regs[regIdx];
670+
Op.Reg.Reg = F32Regs[regIdx];
670671
return true;
671672
}
672673

673674
static bool MorphToF128Reg(VEOperand &Op) {
674-
unsigned Reg = Op.getReg();
675+
MCRegister Reg = Op.getReg();
675676
unsigned regIdx = Reg - VE::SX0;
676677
if (regIdx % 2 || regIdx > 63)
677678
return false;
678-
Op.Reg.RegNum = F128Regs[regIdx / 2];
679+
Op.Reg.Reg = F128Regs[regIdx / 2];
679680
return true;
680681
}
681682

682683
static bool MorphToVM512Reg(VEOperand &Op) {
683-
unsigned Reg = Op.getReg();
684+
MCRegister Reg = Op.getReg();
684685
unsigned regIdx = Reg - VE::VM0;
685686
if (regIdx % 2 || regIdx > 15)
686687
return false;
687-
Op.Reg.RegNum = VM512Regs[regIdx / 2];
688+
Op.Reg.Reg = VM512Regs[regIdx / 2];
688689
return true;
689690
}
690691

@@ -696,16 +697,16 @@ class VEOperand : public MCParsedAsmOperand {
696697
if (regIdx > 31 || MISCRegs[regIdx] == VE::NoRegister)
697698
return false;
698699
Op.Kind = k_Register;
699-
Op.Reg.RegNum = MISCRegs[regIdx];
700+
Op.Reg.Reg = MISCRegs[regIdx];
700701
return true;
701702
}
702703

703704
static std::unique_ptr<VEOperand>
704-
MorphToMEMri(unsigned Base, std::unique_ptr<VEOperand> Op) {
705+
MorphToMEMri(MCRegister Base, std::unique_ptr<VEOperand> Op) {
705706
const MCExpr *Imm = Op->getImm();
706707
Op->Kind = k_MemoryRegImm;
707708
Op->Mem.Base = Base;
708-
Op->Mem.IndexReg = 0;
709+
Op->Mem.IndexReg = MCRegister();
709710
Op->Mem.Index = nullptr;
710711
Op->Mem.Offset = Imm;
711712
return Op;
@@ -715,15 +716,16 @@ class VEOperand : public MCParsedAsmOperand {
715716
MorphToMEMzi(std::unique_ptr<VEOperand> Op) {
716717
const MCExpr *Imm = Op->getImm();
717718
Op->Kind = k_MemoryZeroImm;
718-
Op->Mem.Base = 0;
719-
Op->Mem.IndexReg = 0;
719+
Op->Mem.Base = MCRegister();
720+
Op->Mem.IndexReg = MCRegister();
720721
Op->Mem.Index = nullptr;
721722
Op->Mem.Offset = Imm;
722723
return Op;
723724
}
724725

725726
static std::unique_ptr<VEOperand>
726-
MorphToMEMrri(unsigned Base, unsigned Index, std::unique_ptr<VEOperand> Op) {
727+
MorphToMEMrri(MCRegister Base, MCRegister Index,
728+
std::unique_ptr<VEOperand> Op) {
727729
const MCExpr *Imm = Op->getImm();
728730
Op->Kind = k_MemoryRegRegImm;
729731
Op->Mem.Base = Base;
@@ -734,22 +736,22 @@ class VEOperand : public MCParsedAsmOperand {
734736
}
735737

736738
static std::unique_ptr<VEOperand>
737-
MorphToMEMrii(unsigned Base, const MCExpr *Index,
739+
MorphToMEMrii(MCRegister Base, const MCExpr *Index,
738740
std::unique_ptr<VEOperand> Op) {
739741
const MCExpr *Imm = Op->getImm();
740742
Op->Kind = k_MemoryRegImmImm;
741743
Op->Mem.Base = Base;
742-
Op->Mem.IndexReg = 0;
744+
Op->Mem.IndexReg = MCRegister();
743745
Op->Mem.Index = Index;
744746
Op->Mem.Offset = Imm;
745747
return Op;
746748
}
747749

748750
static std::unique_ptr<VEOperand>
749-
MorphToMEMzri(unsigned Index, std::unique_ptr<VEOperand> Op) {
751+
MorphToMEMzri(MCRegister Index, std::unique_ptr<VEOperand> Op) {
750752
const MCExpr *Imm = Op->getImm();
751753
Op->Kind = k_MemoryZeroRegImm;
752-
Op->Mem.Base = 0;
754+
Op->Mem.Base = MCRegister();
753755
Op->Mem.IndexReg = Index;
754756
Op->Mem.Index = nullptr;
755757
Op->Mem.Offset = Imm;
@@ -760,8 +762,8 @@ class VEOperand : public MCParsedAsmOperand {
760762
MorphToMEMzii(const MCExpr *Index, std::unique_ptr<VEOperand> Op) {
761763
const MCExpr *Imm = Op->getImm();
762764
Op->Kind = k_MemoryZeroImmImm;
763-
Op->Mem.Base = 0;
764-
Op->Mem.IndexReg = 0;
765+
Op->Mem.Base = MCRegister();
766+
Op->Mem.IndexReg = MCRegister();
765767
Op->Mem.Index = Index;
766768
Op->Mem.Offset = Imm;
767769
return Op;
@@ -815,14 +817,14 @@ bool VEAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc,
815817

816818
/// Parses a register name using a given matching function.
817819
/// Checks for lowercase or uppercase if necessary.
818-
int VEAsmParser::parseRegisterName(MCRegister (*matchFn)(StringRef)) {
820+
MCRegister VEAsmParser::parseRegisterName(MCRegister (*matchFn)(StringRef)) {
819821
StringRef Name = Parser.getTok().getString();
820822

821-
int RegNum = matchFn(Name);
823+
MCRegister RegNum = matchFn(Name);
822824

823825
// GCC supports case insensitive register names. All of the VE registers
824826
// are all lower case.
825-
if (RegNum == VE::NoRegister) {
827+
if (!RegNum) {
826828
RegNum = matchFn(Name.lower());
827829
}
828830

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