Add end markers for package and architecture #19
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Signed-off-by: Andrés Manelli <[email protected]>
m-tosch
reviewed
May 27, 2021
hdlparse/vhdl_parser.py
Outdated
| @@ -32,7 +32,8 @@ | |||
| (r'subtype\s+(\w+)\s+is\s+(\w+)', 'subtype'), | |||
| (r'constant\s+(\w+)\s+:\s+(\w+)', 'constant'), | |||
| (r'type\s+(\w+)\s*is', 'type', 'type_decl'), | |||
| (r'end\s+package', None, '#pop'), | |||
| (r'end\s+\w+\s*;', None, '#pop'), | |||
| (r'end\s+package\s+\w+\s*;', None, '#pop'), | |||
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This line has a slightly different matching than the one above. It is probably not needed.
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I'll change that as it is for entity in #14 based on your comment.
m-tosch
reviewed
May 27, 2021
hdlparse/vhdl_parser.py
Outdated
| @@ -89,7 +90,8 @@ | |||
| (r'--.*\n', None), | |||
| ], | |||
| 'architecture': [ | |||
| (r'end\s+architecture\s*;', 'end_arch', '#pop'), | |||
| (r'end\s+\w+\s*;', 'end_arch', '#pop'), | |||
| (r'end\s+architecture\s+\w+\s*;', 'end_arch', '#pop'), | |||
|
Ok, so I left only the \w+ matching (also for package body) |
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Signed-off-by: Andrés Manelli [email protected]