Skip to content

Add support for logic type and fix minor syntax error #15

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 1 commit into
base: master
Choose a base branch
from
Open

Add support for logic type and fix minor syntax error #15

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion hdlparse/minilexer.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@ def __init__(self, tokens, flags=re.MULTILINE):
if new_state and new_state.startswith('#pop'):
try:
new_state = -int(new_state.split(':')[1])
except IndexError, ValueError:
except (IndexError, ValueError):
new_state = -1

full_patterns.append((pat, action, new_state))
Expand Down
4 changes: 2 additions & 2 deletions hdlparse/verilog_parser.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@
],
'module': [
(r'parameter\s*(signed|integer|realtime|real|time)?\s*(\[[^]]+\])?', 'parameter_start', 'parameters'),
(r'(input|inout|output)\s*(reg|supply0|supply1|tri|triand|trior|tri0|tri1|wire|wand|wor)?\s*(signed)?\s*(\[[^]]+\])?', 'module_port_start', 'module_port'),
(r'(input|inout|output)\s*(reg|supply0|supply1|tri|triand|trior|tri0|tri1|wire|wand|wor|logic)?\s*(signed)?\s*(\[[^]]+\])?', 'module_port_start', 'module_port'),
(r'endmodule', 'end_module', '#pop'),
(r'/\*', 'block_comment', 'block_comment'),
(r'//#\s*{{(.*)}}\n', 'section_meta'),
Expand All @@ -30,7 +30,7 @@
(r'[);]', None, '#pop'),
],
'module_port': [
(r'\s*(input|inout|output)\s*(reg|supply0|supply1|tri|triand|trior|tri0|tri1|wire|wand|wor)?\s*(signed)?\s*(\[[^]]+\])?', 'module_port_start'),
(r'\s*(input|inout|output)\s*(reg|supply0|supply1|tri|triand|trior|tri0|tri1|wire|wand|wor|logic)?\s*(signed)?\s*(\[[^]]+\])?', 'module_port_start'),
(r'\s*(\w+)\s*,?', 'port_param'),
(r'[);]', None, '#pop'),
(r'//#\s*{{(.*)}}\n', 'section_meta'),
Expand Down