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jimaandro/README.md

Hi 👋, I'm Dimitris

A passionate hardware design engineer with a background in FPGA design, SoC integration, and processor architectures. I hold an Integrated Master’s degree in Electrical and Computer Engineering from Aristotle University of Thessaloniki (AUTH) and I am currently pursuing a Master’s in Computer Science at the University of Crete.

Connect with me:

dimitris-andronikou

Languages and Tools:

Verilog SystemVerilog Xilinx Vivado Synopsys VCS Cadence Genus cplusplus c cplusplus java git docker kubernetes linux

jimaandro

 jimaandro

jimaandro

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  1. JTAG_TO_AXI JTAG_TO_AXI Public

    These scripts are used in a Vivado project, to implement jtag to axi transactions. The general project is to run baremetal cpp code on Ariane RISC-V core

    Tcl 2

  2. project-1 project-1 Public

    This is an implementation of a floating point numbers ALU, according to IEEE-754 standard

    VHDL 1

  3. MIPS_processor MIPS_processor Public

    This is a university project. It is an implementation ant testing of MIPS processor in verilog.

    C 1

  4. e-left/advanced_computer_architecture_lab2 e-left/advanced_computer_architecture_lab2 Public

    Lab reports, along with code samples and statistics for the Advanced Computer Architecture course

    Shell

  5. e-left/advanced_computer_architecture_lab1 e-left/advanced_computer_architecture_lab1 Public

    Lab reports, along with code samples and statistics for the Advanced Computer Architecture course

    C

  6. generic_flP_alu generic_flP_alu Public

    Tcl 2