[SYCL][FPGA]Implementation of max_reinvocation_delay loop attribute #6623
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bowenxue-intel
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Fznamznon
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Aug 23, 2022
premanandrao
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Aug 23, 2022
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@intel/llvm-gatekeepers This PR is ready for review and merge |
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Add support for max_reinvocation_delay FPGA loop attribute, used for specifying the maximum number of cycles allowed between loop invocations.