[SYCL][DOC] Add extension for FPGA kernel interface properties

[tiwaria1]

SYCL extension contains the following new kernel properties

• streaming_interface<...>
• register_map_interface<...>
  The first two properties take enum arguments that provide the compiler information about whether the logic downstream to the kernel will back-pressure the kernel or not.
• pipelined<N>
  Takes an integer, non-zero values specify minimum cycles between kernel invocations, and 0 specifies that pipelining should be disabled.

[GarveyJoe]

I would drop the mention of RTL. It confuses things to refer to the description of the hardware as being separate from the hardware itself.
Also, I think your intent is for this to apply to both control and data signals. Can you state the explicitly? And assuming that this should apply to data signals as well, should it apply to all inputs/outputs from the kernel, i.e. pipes as well, or only kernel arguments?

[tiwaria1]

Added explicit statement. Specified that it should apply to kernel arguments and control flow signals only. Including pipes seems to make sense. I need to think a bit more about including them.

[keryell]

Is this a magic function that encode the properties? How it is connected to the single_task below?

[keryell]

Do you mean several instances of a single_task or this is pipelining at the work-item level?

[GarveyJoe]

This refers to several instances of a kernel, most commonly a single_task kernel. It does not refer to pipelining of work-items. However, there's no reason this couldn't be applied to a parallel_for kernel to request that successive launches of that kernel be pipelined in addition to the usual work item pipelining. In such a kernel, the work items could be injected into the datapath one after another and, after the last work item from a given kernel invocation has been injected, the first work-item of the next invocation could be injected without waiting for the pipeline to drain.

I don't see much value in a control to enable or disable pipelining at the work-item level because that's nearly always beneficial. This invocation pipelining is more situational though as it only provides value if the user intends to launch the same kernel multiple times.

[tiwaria1]

ping @intel/dpcpp-specification-reviewers

[steffenlarsen]

LGTM!

[keryell]

pipelined could be simplified to take a single parameter with value false, true or some II value.
The current cartesian product with 2 parameters is useless since false and an II is meaningless.

[keryell]

Also having a default true value for the pipelined when used seems an interesting shortcut.

[GarveyJoe]

Links are broken

[tiwaria1]

They seem to be working now.
oneapi properties is in experimental folder: https://github.com/intel/llvm/tree/sycl/sycl/doc/extensions/experimental
and oneapi kernel properties will be in the proposed folder after 5755 PR goes in : https://github.com/intel/llvm/pull/5755/files

[tiwaria1]

@steffenlarsen I addressed the remaining comments. Please review and merge this PR. Based on your namespace comment on a different PR I have updated the namespace here to be sycl::ext::intel::experimental since this is a FPGA specific extension.

[steffenlarsen]

Just a few more comments, then I think I'm happy!

[tiwaria1]

Just a few more comments, then I think I'm happy!

Hey Steffen, I addressed the other comments. Please take a look.

[steffenlarsen]

LGTM!