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[libspirv] Use the remangler to mangle half types #18083

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Merged
merged 5 commits into from
Apr 23, 2025
Merged

[libspirv] Use the remangler to mangle half types #18083

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8a20e09
[libspirv][AMD] Fix sub-group shuffle builtins
frasercrmck Apr 17, 2025
c322440
use existing types
frasercrmck Apr 17, 2025
38e0b95
wip: remangle dh -> df16_
frasercrmck Apr 21, 2025
798f8a8
fix this one builtin?
frasercrmck Apr 22, 2025
1af339a
Merge remote-tracking branch 'origin/sycl' into libspirv-amd-subgroup…
frasercrmck Apr 23, 2025
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9 changes: 0 additions & 9 deletions libclc/generic/include/as_type.h
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Original file line number Diff line number Diff line change
Expand Up @@ -85,13 +85,4 @@
#define as_half16(x) __builtin_astype(x, half16)
#endif

#ifdef __CLC_HAS_FLOAT16
#define as_float16_t(x) __builtin_astype(x, __clc_float16_t)
#define as_vec2_float16_t(x) __builtin_astype(x, __clc_vec2_float16_t)
#define as_vec3_float16_t(x) __builtin_astype(x, __clc_vec3_float16_t)
#define as_vec4_float16_t(x) __builtin_astype(x, __clc_vec4_float16_t)
#define as_vec8_float16_t(x) __builtin_astype(x, __clc_vec8_float16_t)
#define as_vec16_float16_t(x) __builtin_astype(x, __clc_vec16_float16_t)
#endif

#endif // CLC_AS_TYPE
14 changes: 1 addition & 13 deletions libclc/libspirv/lib/amdgcn-amdhsa/group/collectives.cl
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Original file line number Diff line number Diff line change
Expand Up @@ -316,18 +316,6 @@ __CLC_GROUP_COLLECTIVE(BitwiseXorKHR, __CLC_XOR, long, 0l)
__CLC_GROUP_COLLECTIVE(LogicalOrKHR, __CLC_LOGICAL_OR, bool, false)
__CLC_GROUP_COLLECTIVE(LogicalAndKHR, __CLC_LOGICAL_AND, bool, true)

// half requires additional mangled entry points
#define __CLC_GROUP_COLLECTIVE__DF16(MANGLED_NAME, SPIRV_DISPATCH) \
_CLC_DEF _CLC_CONVERGENT half MANGLED_NAME(int scope, uint op, half x) { \
return SPIRV_DISPATCH(scope, op, x); \
}
__CLC_GROUP_COLLECTIVE__DF16(_Z17__spirv_GroupFAddiiDF16_, __spirv_GroupFAdd)
__CLC_GROUP_COLLECTIVE__DF16(_Z17__spirv_GroupFMiniiDF16_, __spirv_GroupFMin)
__CLC_GROUP_COLLECTIVE__DF16(_Z17__spirv_GroupFMaxiiDF16_, __spirv_GroupFMax)
__CLC_GROUP_COLLECTIVE__DF16(_Z20__spirv_GroupFMulKHRiiDF16_,
__spirv_GroupFMulKHR)
#undef __CLC_GROUP_COLLECTIVE__DF16

#undef __CLC_GROUP_COLLECTIVE_4
#undef __CLC_GROUP_COLLECTIVE_5
#undef DISPATCH_TO_CLC_GROUP_COLLECTIVE_MACRO
Expand Down Expand Up @@ -391,7 +379,7 @@ __CLC_GROUP_BROADCAST(int, i)
__CLC_GROUP_BROADCAST(uint, j)
__CLC_GROUP_BROADCAST(long, l)
__CLC_GROUP_BROADCAST(ulong, m)
__CLC_GROUP_BROADCAST(half, DF16_)
__CLC_GROUP_BROADCAST(half, Dh)
__CLC_GROUP_BROADCAST(float, f)
__CLC_GROUP_BROADCAST(double, d)

Expand Down
54 changes: 27 additions & 27 deletions libclc/libspirv/lib/amdgcn-amdhsa/images/image.cl
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Expand Up @@ -94,17 +94,17 @@ _CLC_DEFINE_IMAGE_BINDLESS_FETCH_32_BUILTIN(3, float4, Dv4_f, int3, Dv3_i)
// Half
#ifdef cl_khr_fp16
// return 1-channel color data
_CLC_DEFINE_IMAGE_BINDLESS_FETCH_16_BUILTIN(1, half, DF16_, int, i)
_CLC_DEFINE_IMAGE_BINDLESS_FETCH_16_BUILTIN(2, half, DF16_, int2, Dv2_i)
_CLC_DEFINE_IMAGE_BINDLESS_FETCH_16_BUILTIN(3, half, DF16_, int3, Dv3_i)
_CLC_DEFINE_IMAGE_BINDLESS_FETCH_16_BUILTIN(1, half, Dh, int, i)
_CLC_DEFINE_IMAGE_BINDLESS_FETCH_16_BUILTIN(2, half, Dh, int2, Dv2_i)
_CLC_DEFINE_IMAGE_BINDLESS_FETCH_16_BUILTIN(3, half, Dh, int3, Dv3_i)
// return 2-channel color data
_CLC_DEFINE_IMAGE_BINDLESS_FETCH_16_BUILTIN(1, half2, Dv2_DF16_, int, i)
_CLC_DEFINE_IMAGE_BINDLESS_FETCH_16_BUILTIN(2, half2, Dv2_DF16_, int2, Dv2_i)
_CLC_DEFINE_IMAGE_BINDLESS_FETCH_16_BUILTIN(3, half2, Dv2_DF16_, int3, Dv3_i)
_CLC_DEFINE_IMAGE_BINDLESS_FETCH_16_BUILTIN(1, half2, Dv2_Dh, int, i)
_CLC_DEFINE_IMAGE_BINDLESS_FETCH_16_BUILTIN(2, half2, Dv2_Dh, int2, Dv2_i)
_CLC_DEFINE_IMAGE_BINDLESS_FETCH_16_BUILTIN(3, half2, Dv2_Dh, int3, Dv3_i)
// return 4-channel color data
_CLC_DEFINE_IMAGE_BINDLESS_FETCH_16_BUILTIN(1, half4, Dv4_DF16_, int, i)
_CLC_DEFINE_IMAGE_BINDLESS_FETCH_16_BUILTIN(2, half4, Dv4_DF16_, int2, Dv2_i)
_CLC_DEFINE_IMAGE_BINDLESS_FETCH_16_BUILTIN(3, half4, Dv4_DF16_, int3, Dv3_i)
_CLC_DEFINE_IMAGE_BINDLESS_FETCH_16_BUILTIN(1, half4, Dv4_Dh, int, i)
_CLC_DEFINE_IMAGE_BINDLESS_FETCH_16_BUILTIN(2, half4, Dv4_Dh, int2, Dv2_i)
_CLC_DEFINE_IMAGE_BINDLESS_FETCH_16_BUILTIN(3, half4, Dv4_Dh, int3, Dv3_i)
#endif

// Int
Expand Down Expand Up @@ -243,17 +243,17 @@ _CLC_DEFINE_IMAGE_BINDLESS_WRITE_32_BUILTIN(3, float4, Dv4_f, int3, Dv3_i)
// Half
#ifdef cl_khr_fp16
// write 1-channel color data
_CLC_DEFINE_IMAGE_BINDLESS_WRITE_16_BUILTIN(1, half, DF16_, int, i)
_CLC_DEFINE_IMAGE_BINDLESS_WRITE_16_BUILTIN(2, half, DF16_, int2, Dv2_i)
_CLC_DEFINE_IMAGE_BINDLESS_WRITE_16_BUILTIN(3, half, DF16_, int3, Dv3_i)
_CLC_DEFINE_IMAGE_BINDLESS_WRITE_16_BUILTIN(1, half, Dh, int, i)
_CLC_DEFINE_IMAGE_BINDLESS_WRITE_16_BUILTIN(2, half, Dh, int2, Dv2_i)
_CLC_DEFINE_IMAGE_BINDLESS_WRITE_16_BUILTIN(3, half, Dh, int3, Dv3_i)
// write 2-channel color data
_CLC_DEFINE_IMAGE_BINDLESS_WRITE_16_BUILTIN(1, half2, Dv2_DF16_, int, i)
_CLC_DEFINE_IMAGE_BINDLESS_WRITE_16_BUILTIN(2, half2, Dv2_DF16_, int2, Dv2_i)
_CLC_DEFINE_IMAGE_BINDLESS_WRITE_16_BUILTIN(3, half2, Dv2_DF16_, int3, Dv3_i)
_CLC_DEFINE_IMAGE_BINDLESS_WRITE_16_BUILTIN(1, half2, Dv2_Dh, int, i)
_CLC_DEFINE_IMAGE_BINDLESS_WRITE_16_BUILTIN(2, half2, Dv2_Dh, int2, Dv2_i)
_CLC_DEFINE_IMAGE_BINDLESS_WRITE_16_BUILTIN(3, half2, Dv2_Dh, int3, Dv3_i)
// write 4-channel color data
_CLC_DEFINE_IMAGE_BINDLESS_WRITE_16_BUILTIN(1, half4, Dv4_DF16_, int, i)
_CLC_DEFINE_IMAGE_BINDLESS_WRITE_16_BUILTIN(2, half4, Dv4_DF16_, int2, Dv2_i)
_CLC_DEFINE_IMAGE_BINDLESS_WRITE_16_BUILTIN(3, half4, Dv4_DF16_, int3, Dv3_i)
_CLC_DEFINE_IMAGE_BINDLESS_WRITE_16_BUILTIN(1, half4, Dv4_Dh, int, i)
_CLC_DEFINE_IMAGE_BINDLESS_WRITE_16_BUILTIN(2, half4, Dv4_Dh, int2, Dv2_i)
_CLC_DEFINE_IMAGE_BINDLESS_WRITE_16_BUILTIN(3, half4, Dv4_Dh, int3, Dv3_i)
#endif

// Int
Expand Down Expand Up @@ -401,20 +401,20 @@ _CLC_DEFINE_SAMPLEDIMAGE_BINDLESS_READ_32_BUILTIN(3, float4, Dv4_f, float3,
// Half
#ifdef cl_khr_fp16
// return 1 channel color data
_CLC_DEFINE_SAMPLEDIMAGE_BINDLESS_READ_16_BUILTIN(1, half, DF16_, float, f)
_CLC_DEFINE_SAMPLEDIMAGE_BINDLESS_READ_16_BUILTIN(2, half, DF16_, float2, Dv2_f)
_CLC_DEFINE_SAMPLEDIMAGE_BINDLESS_READ_16_BUILTIN(3, half, DF16_, float3, Dv3_f)
_CLC_DEFINE_SAMPLEDIMAGE_BINDLESS_READ_16_BUILTIN(1, half, Dh, float, f)
_CLC_DEFINE_SAMPLEDIMAGE_BINDLESS_READ_16_BUILTIN(2, half, Dh, float2, Dv2_f)
_CLC_DEFINE_SAMPLEDIMAGE_BINDLESS_READ_16_BUILTIN(3, half, Dh, float3, Dv3_f)
// return 2-channel color data
_CLC_DEFINE_SAMPLEDIMAGE_BINDLESS_READ_16_BUILTIN(1, half2, Dv2_DF16_, float, f)
_CLC_DEFINE_SAMPLEDIMAGE_BINDLESS_READ_16_BUILTIN(2, half2, Dv2_DF16_, float2,
_CLC_DEFINE_SAMPLEDIMAGE_BINDLESS_READ_16_BUILTIN(1, half2, Dv2_Dh, float, f)
_CLC_DEFINE_SAMPLEDIMAGE_BINDLESS_READ_16_BUILTIN(2, half2, Dv2_Dh, float2,
Dv2_f)
_CLC_DEFINE_SAMPLEDIMAGE_BINDLESS_READ_16_BUILTIN(3, half2, Dv2_DF16_, float3,
_CLC_DEFINE_SAMPLEDIMAGE_BINDLESS_READ_16_BUILTIN(3, half2, Dv2_Dh, float3,
Dv3_f)
// return 4-channel color data
_CLC_DEFINE_SAMPLEDIMAGE_BINDLESS_READ_16_BUILTIN(1, half4, Dv4_DF16_, float, f)
_CLC_DEFINE_SAMPLEDIMAGE_BINDLESS_READ_16_BUILTIN(2, half4, Dv4_DF16_, float2,
_CLC_DEFINE_SAMPLEDIMAGE_BINDLESS_READ_16_BUILTIN(1, half4, Dv4_Dh, float, f)
_CLC_DEFINE_SAMPLEDIMAGE_BINDLESS_READ_16_BUILTIN(2, half4, Dv4_Dh, float2,
Dv2_f)
_CLC_DEFINE_SAMPLEDIMAGE_BINDLESS_READ_16_BUILTIN(3, half4, Dv4_DF16_, float3,
_CLC_DEFINE_SAMPLEDIMAGE_BINDLESS_READ_16_BUILTIN(3, half4, Dv4_Dh, float3,
Dv3_f)
#endif

Expand Down
36 changes: 18 additions & 18 deletions libclc/libspirv/lib/amdgcn-amdhsa/images/image_array.cl
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Original file line number Diff line number Diff line change
Expand Up @@ -88,18 +88,18 @@ _CLC_DEFINE_IMAGE_ARRAY_BINDLESS_FETCH_32_BUILTIN(2, float4, Dv4_f, int2, Dv2_i,
// Half
#ifdef cl_khr_fp16
// return 1-channel color data
_CLC_DEFINE_IMAGE_ARRAY_BINDLESS_FETCH_16_BUILTIN(1, half, DF16_, int, i, 2)
_CLC_DEFINE_IMAGE_ARRAY_BINDLESS_FETCH_16_BUILTIN(2, half, DF16_, int2, Dv2_i,
_CLC_DEFINE_IMAGE_ARRAY_BINDLESS_FETCH_16_BUILTIN(1, half, Dh, int, i, 2)
_CLC_DEFINE_IMAGE_ARRAY_BINDLESS_FETCH_16_BUILTIN(2, half, Dh, int2, Dv2_i,
4)
// return 2-channel color data
_CLC_DEFINE_IMAGE_ARRAY_BINDLESS_FETCH_16_BUILTIN(1, half2, Dv2_DF16_, int, i,
_CLC_DEFINE_IMAGE_ARRAY_BINDLESS_FETCH_16_BUILTIN(1, half2, Dv2_Dh, int, i,
2)
_CLC_DEFINE_IMAGE_ARRAY_BINDLESS_FETCH_16_BUILTIN(2, half2, Dv2_DF16_, int2,
_CLC_DEFINE_IMAGE_ARRAY_BINDLESS_FETCH_16_BUILTIN(2, half2, Dv2_Dh, int2,
Dv2_i, 4)
// return 4-channel color data
_CLC_DEFINE_IMAGE_ARRAY_BINDLESS_FETCH_16_BUILTIN(1, half4, Dv4_DF16_, int, i,
_CLC_DEFINE_IMAGE_ARRAY_BINDLESS_FETCH_16_BUILTIN(1, half4, Dv4_Dh, int, i,
2)
_CLC_DEFINE_IMAGE_ARRAY_BINDLESS_FETCH_16_BUILTIN(2, half4, Dv4_DF16_, int2,
_CLC_DEFINE_IMAGE_ARRAY_BINDLESS_FETCH_16_BUILTIN(2, half4, Dv4_Dh, int2,
Dv2_i, 4)
#endif

Expand Down Expand Up @@ -237,18 +237,18 @@ _CLC_DEFINE_IMAGE_ARRAY_BINDLESS_WRITE_32_BUILTIN(2, float4, Dv4_f, int2, Dv2_i,
// Half
#ifdef cl_khr_fp16
// write 1-channel color data
_CLC_DEFINE_IMAGE_ARRAY_BINDLESS_WRITE_16_BUILTIN(1, half, DF16_, int, i, 2)
_CLC_DEFINE_IMAGE_ARRAY_BINDLESS_WRITE_16_BUILTIN(2, half, DF16_, int2, Dv2_i,
_CLC_DEFINE_IMAGE_ARRAY_BINDLESS_WRITE_16_BUILTIN(1, half, Dh, int, i, 2)
_CLC_DEFINE_IMAGE_ARRAY_BINDLESS_WRITE_16_BUILTIN(2, half, Dh, int2, Dv2_i,
4)
// write 2-channel color data
_CLC_DEFINE_IMAGE_ARRAY_BINDLESS_WRITE_16_BUILTIN(1, half2, Dv2_DF16_, int, i,
_CLC_DEFINE_IMAGE_ARRAY_BINDLESS_WRITE_16_BUILTIN(1, half2, Dv2_Dh, int, i,
2)
_CLC_DEFINE_IMAGE_ARRAY_BINDLESS_WRITE_16_BUILTIN(2, half2, Dv2_DF16_, int2,
_CLC_DEFINE_IMAGE_ARRAY_BINDLESS_WRITE_16_BUILTIN(2, half2, Dv2_Dh, int2,
Dv2_i, 4)
// write 4-channel color data
_CLC_DEFINE_IMAGE_ARRAY_BINDLESS_WRITE_16_BUILTIN(1, half4, Dv4_DF16_, int, i,
_CLC_DEFINE_IMAGE_ARRAY_BINDLESS_WRITE_16_BUILTIN(1, half4, Dv4_Dh, int, i,
2)
_CLC_DEFINE_IMAGE_ARRAY_BINDLESS_WRITE_16_BUILTIN(2, half4, Dv4_DF16_, int2,
_CLC_DEFINE_IMAGE_ARRAY_BINDLESS_WRITE_16_BUILTIN(2, half4, Dv4_Dh, int2,
Dv2_i, 4)
#endif

Expand Down Expand Up @@ -395,19 +395,19 @@ _CLC_DEFINE_SAMPLEDIMAGE_ARRAY_BINDLESS_READ_32_BUILTIN(2, float4, Dv4_f,
// Half
#ifdef cl_khr_fp16
// return 1 channel color data
_CLC_DEFINE_SAMPLEDIMAGE_ARRAY_BINDLESS_READ_16_BUILTIN(1, half, DF16_, float,
_CLC_DEFINE_SAMPLEDIMAGE_ARRAY_BINDLESS_READ_16_BUILTIN(1, half, Dh, float,
f, 2)
_CLC_DEFINE_SAMPLEDIMAGE_ARRAY_BINDLESS_READ_16_BUILTIN(2, half, DF16_, float2,
_CLC_DEFINE_SAMPLEDIMAGE_ARRAY_BINDLESS_READ_16_BUILTIN(2, half, Dh, float2,
Dv2_f, 4)
// return 2 channel color data
_CLC_DEFINE_SAMPLEDIMAGE_ARRAY_BINDLESS_READ_16_BUILTIN(1, half2, Dv2_DF16_,
_CLC_DEFINE_SAMPLEDIMAGE_ARRAY_BINDLESS_READ_16_BUILTIN(1, half2, Dv2_Dh,
float, f, 2)
_CLC_DEFINE_SAMPLEDIMAGE_ARRAY_BINDLESS_READ_16_BUILTIN(2, half2, Dv2_DF16_,
_CLC_DEFINE_SAMPLEDIMAGE_ARRAY_BINDLESS_READ_16_BUILTIN(2, half2, Dv2_Dh,
float2, Dv2_f, 4)
// return 4 channel color data
_CLC_DEFINE_SAMPLEDIMAGE_ARRAY_BINDLESS_READ_16_BUILTIN(1, half4, Dv4_DF16_,
_CLC_DEFINE_SAMPLEDIMAGE_ARRAY_BINDLESS_READ_16_BUILTIN(1, half4, Dv4_Dh,
float, f, 2)
_CLC_DEFINE_SAMPLEDIMAGE_ARRAY_BINDLESS_READ_16_BUILTIN(2, half4, Dv4_DF16_,
_CLC_DEFINE_SAMPLEDIMAGE_ARRAY_BINDLESS_READ_16_BUILTIN(2, half4, Dv4_Dh,
float2, Dv2_f, 4)
#endif

Expand Down
62 changes: 31 additions & 31 deletions libclc/libspirv/lib/amdgcn-amdhsa/misc/sub_group_shuffle.cl
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Expand Up @@ -39,7 +39,7 @@ __AMDGCN_CLC_SUBGROUP_SUB_I32(unsigned short);
// _Z28__spirv_SubgroupShuffleINTELIhET_S0_j - unsigned char
// _Z28__spirv_SubgroupShuffleINTELIsET_S0_j - long
// _Z28__spirv_SubgroupShuffleINTELItET_S0_j - unsigned long
// _Z28__spirv_SubgroupShuffleINTELIDF16_ET_S0_j - half
// _Z28__spirv_SubgroupShuffleINTELIDhET_S0_j - half
#define __AMDGCN_CLC_SUBGROUP_SUB_I32(TYPE, MANGLED_TYPE_NAME) \
_CLC_DEF TYPE _Z28__spirv_SubgroupShuffleINTELI##MANGLED_TYPE_NAME##ET_S0_j( \
TYPE Data, unsigned int InvocationId) { \
Expand All @@ -58,7 +58,7 @@ __spirv_SubgroupShuffleINTEL(half Data, unsigned int InvocationId) {
tmp = __spirv_SubgroupShuffleINTEL(tmp, InvocationId);
return __clc_as_half(tmp);
}
_CLC_DEF half _Z28__spirv_SubgroupShuffleINTELIDF16_ET_S0_j(
_CLC_DEF half _Z28__spirv_SubgroupShuffleINTELIDhET_S0_j(
half Data, unsigned int InvocationId) {
return __spirv_SubgroupShuffleINTEL(Data, InvocationId);
}
Expand Down Expand Up @@ -227,10 +227,10 @@ __AMDGCN_CLC_SUBGROUP_TO_VEC(ulong8, m, 8)
__AMDGCN_CLC_SUBGROUP_TO_VEC(ulong16, m, 16)
// half
#ifdef cl_khr_fp16
__AMDGCN_CLC_SUBGROUP_TO_VEC(half2, DF16_, 2)
__AMDGCN_CLC_SUBGROUP_TO_VEC(half4, DF16_, 4)
__AMDGCN_CLC_SUBGROUP_TO_VEC(half8, DF16_, 8)
__AMDGCN_CLC_SUBGROUP_TO_VEC(half16, DF16_, 16)
__AMDGCN_CLC_SUBGROUP_TO_VEC(half2, Dh, 2)
__AMDGCN_CLC_SUBGROUP_TO_VEC(half4, Dh, 4)
__AMDGCN_CLC_SUBGROUP_TO_VEC(half8, Dh, 8)
__AMDGCN_CLC_SUBGROUP_TO_VEC(half16, Dh, 16)
#endif // cl_khr_fp16
// float
__AMDGCN_CLC_SUBGROUP_TO_VEC(float2, f, 2)
Expand Down Expand Up @@ -271,8 +271,8 @@ __AMDGCN_CLC_SUBGROUP_XOR_SUB_I32(unsigned char);
__AMDGCN_CLC_SUBGROUP_XOR_SUB_I32(short);
__AMDGCN_CLC_SUBGROUP_XOR_SUB_I32(unsigned short);
#ifdef cl_khr_fp16
_CLC_OVERLOAD _CLC_DEF half
__spirv_SubgroupShuffleXorINTEL(half Data, unsigned int InvocationId) {
_CLC_OVERLOAD _CLC_DEF half __spirv_SubgroupShuffleXorINTEL(
half Data, unsigned int InvocationId) {
unsigned short tmp = __clc_as_ushort(Data);
tmp = (unsigned short)__spirv_SubgroupShuffleXorINTEL(tmp, InvocationId);
return __clc_as_half(tmp);
Expand All @@ -284,7 +284,7 @@ __spirv_SubgroupShuffleXorINTEL(half Data, unsigned int InvocationId) {
// _Z31__spirv_SubgroupShuffleXorINTELIhET_S0_j - unsigned char
// _Z31__spirv_SubgroupShuffleXorINTELIsET_S0_j - short
// _Z31__spirv_SubgroupShuffleXorINTELItET_S0_j - unsigned short
// _Z31__spirv_SubgroupShuffleXorINTELIDF16_ET_S0_j - half
// _Z31__spirv_SubgroupShuffleXorINTELIDhET_S0_j - half
#define __AMDGCN_CLC_SUBGROUP_XOR_SUB_I32(TYPE, MANGLED_TYPE_NAME) \
_CLC_DEF TYPE \
_Z31__spirv_SubgroupShuffleXorINTELI##MANGLED_TYPE_NAME##ET_S0_j( \
Expand All @@ -296,7 +296,7 @@ __AMDGCN_CLC_SUBGROUP_XOR_SUB_I32(unsigned char, h);
__AMDGCN_CLC_SUBGROUP_XOR_SUB_I32(short, s);
__AMDGCN_CLC_SUBGROUP_XOR_SUB_I32(unsigned short, t);
#ifdef cl_khr_fp16
_CLC_DEF half _Z31__spirv_SubgroupShuffleXorINTELIDF16_ET_S0_j(
_CLC_DEF half _Z31__spirv_SubgroupShuffleXorINTELIDhET_S0_j(
half Data, unsigned int InvocationId) {
return __spirv_SubgroupShuffleXorINTEL(Data, InvocationId);
}
Expand Down Expand Up @@ -470,10 +470,10 @@ __AMDGCN_CLC_SUBGROUP_XOR_TO_VEC(float8, f, 8)
__AMDGCN_CLC_SUBGROUP_XOR_TO_VEC(float16, f, 16)
// half
#ifdef cl_khr_fp16
__AMDGCN_CLC_SUBGROUP_XOR_TO_VEC(half2, DF16_, 2)
__AMDGCN_CLC_SUBGROUP_XOR_TO_VEC(half4, DF16_, 4)
__AMDGCN_CLC_SUBGROUP_XOR_TO_VEC(half8, DF16_, 8)
__AMDGCN_CLC_SUBGROUP_XOR_TO_VEC(half16, DF16_, 16)
__AMDGCN_CLC_SUBGROUP_XOR_TO_VEC(half2, Dh, 2)
__AMDGCN_CLC_SUBGROUP_XOR_TO_VEC(half4, Dh, 4)
__AMDGCN_CLC_SUBGROUP_XOR_TO_VEC(half8, Dh, 8)
__AMDGCN_CLC_SUBGROUP_XOR_TO_VEC(half16, Dh, 16)
#endif // cl_khr_fp16
// double
__AMDGCN_CLC_SUBGROUP_XOR_TO_VEC(double2, d, 2)
Expand Down Expand Up @@ -521,11 +521,11 @@ __AMDGCN_CLC_SUBGROUP_UP_SUB_I32(char);
__AMDGCN_CLC_SUBGROUP_UP_SUB_I32(unsigned char);
__AMDGCN_CLC_SUBGROUP_UP_SUB_I32(short);
__AMDGCN_CLC_SUBGROUP_UP_SUB_I32(unsigned short);

// half
#ifdef cl_khr_fp16
_CLC_OVERLOAD _CLC_DEF half __spirv_SubgroupShuffleUpINTEL(half previous,
half current,
unsigned int delta) {
_CLC_OVERLOAD _CLC_DEF half __spirv_SubgroupShuffleUpINTEL(
half previous, half current, unsigned int delta) {
unsigned short tmpP = __clc_as_ushort(previous);
unsigned short tmpC = __clc_as_ushort(current);
tmpC = __spirv_SubgroupShuffleUpINTEL(tmpP, tmpC, delta);
Expand All @@ -538,7 +538,7 @@ _CLC_OVERLOAD _CLC_DEF half __spirv_SubgroupShuffleUpINTEL(half previous,
// _Z30__spirv_SubgroupShuffleUpINTELIhET_S0_S0_j - unsigned char
// _Z30__spirv_SubgroupShuffleUpINTELIsET_S0_S0_j - short
// _Z30__spirv_SubgroupShuffleUpINTELItET_S0_S0_j - unsigned short
// _Z30__spirv_SubgroupShuffleUpINTELIDF16_ET_S0_S0_j - half
// _Z30__spirv_SubgroupShuffleUpINTELIDhET_S0_S0_j - half
#define __AMDGCN_CLC_SUBGROUP_UP_SUB_I32(TYPE, MANGLED_TYPE_NAME) \
_CLC_DEF TYPE \
_Z30__spirv_SubgroupShuffleUpINTELI##MANGLED_TYPE_NAME##ET_S0_S0_j( \
Expand All @@ -551,7 +551,7 @@ __AMDGCN_CLC_SUBGROUP_UP_SUB_I32(short, s);
__AMDGCN_CLC_SUBGROUP_UP_SUB_I32(unsigned short, t);
// half
#ifdef cl_khr_fp16
_CLC_DEF half _Z30__spirv_SubgroupShuffleUpINTELIDF16_ET_S0_S0_j(
_CLC_DEF half _Z30__spirv_SubgroupShuffleUpINTELIDhET_S0_S0_j(
half previous, half current, unsigned int delta) {
return __spirv_SubgroupShuffleUpINTEL(previous, current, delta);
}
Expand Down Expand Up @@ -724,10 +724,10 @@ __AMDGCN_CLC_SUBGROUP_UP_TO_VEC(ulong8, m, 8)
__AMDGCN_CLC_SUBGROUP_UP_TO_VEC(ulong16, m, 16)
// half
#ifdef cl_khr_fp16
__AMDGCN_CLC_SUBGROUP_UP_TO_VEC(half2, DF16_, 2)
__AMDGCN_CLC_SUBGROUP_UP_TO_VEC(half4, DF16_, 4)
__AMDGCN_CLC_SUBGROUP_UP_TO_VEC(half8, DF16_, 8)
__AMDGCN_CLC_SUBGROUP_UP_TO_VEC(half16, DF16_, 16)
__AMDGCN_CLC_SUBGROUP_UP_TO_VEC(half2, Dh, 2)
__AMDGCN_CLC_SUBGROUP_UP_TO_VEC(half4, Dh, 4)
__AMDGCN_CLC_SUBGROUP_UP_TO_VEC(half8, Dh, 8)
__AMDGCN_CLC_SUBGROUP_UP_TO_VEC(half16, Dh, 16)
#endif // cl_khr_fp16
// float
__AMDGCN_CLC_SUBGROUP_UP_TO_VEC(float2, f, 2)
Expand Down Expand Up @@ -782,8 +782,8 @@ __AMDGCN_CLC_SUBGROUP_DOWN_TO_I32(short);
__AMDGCN_CLC_SUBGROUP_DOWN_TO_I32(unsigned short);
// half
#ifdef cl_khr_fp16
_CLC_OVERLOAD _CLC_DEF half
__spirv_SubgroupShuffleDownINTEL(half current, half next, unsigned int delta) {
_CLC_OVERLOAD _CLC_DEF half __spirv_SubgroupShuffleDownINTEL(
half current, half next, unsigned int delta) {
unsigned short tmpC = __clc_as_ushort(current);
unsigned short tmpN = __clc_as_ushort(next);
tmpC = __spirv_SubgroupShuffleDownINTEL(tmpC, tmpN, delta);
Expand All @@ -796,7 +796,7 @@ __spirv_SubgroupShuffleDownINTEL(half current, half next, unsigned int delta) {
// _Z32__spirv_SubgroupShuffleDownINTELIhET_S0_S0_j - unsigned char
// _Z32__spirv_SubgroupShuffleDownINTELIsET_S0_S0_j - short
// _Z32__spirv_SubgroupShuffleDownINTELItET_S0_S0_j - unsigned short
// _Z32__spirv_SubgroupShuffleDownINTELIDF16_ET_S0_S0_j - half
// _Z32__spirv_SubgroupShuffleDownINTELIDhET_S0_S0_j - half
#define __AMDGCN_CLC_SUBGROUP_DOWN_TO_I32(TYPE, MANGLED_TYPE_NAME) \
_CLC_DEF TYPE \
_Z32__spirv_SubgroupShuffleDownINTELI##MANGLED_TYPE_NAME##ET_S0_S0_j( \
Expand All @@ -809,7 +809,7 @@ __AMDGCN_CLC_SUBGROUP_DOWN_TO_I32(short, s);
__AMDGCN_CLC_SUBGROUP_DOWN_TO_I32(unsigned short, t);
// half
#ifdef cl_khr_fp16
_CLC_DEF half _Z32__spirv_SubgroupShuffleDownINTELIDF16_ET_S0_S0_j(
_CLC_DEF half _Z32__spirv_SubgroupShuffleDownINTELIDhET_S0_S0_j(
half current, half next, unsigned int delta) {
return __spirv_SubgroupShuffleDownINTEL(current, next, delta);
}
Expand Down Expand Up @@ -980,10 +980,10 @@ __AMDGCN_CLC_SUBGROUP_DOWN_TO_VEC(ulong8, m, 8)
__AMDGCN_CLC_SUBGROUP_DOWN_TO_VEC(ulong16, m, 16)
// half
#ifdef cl_khr_fp16
__AMDGCN_CLC_SUBGROUP_DOWN_TO_VEC(half2, DF16_, 2)
__AMDGCN_CLC_SUBGROUP_DOWN_TO_VEC(half4, DF16_, 4)
__AMDGCN_CLC_SUBGROUP_DOWN_TO_VEC(half8, DF16_, 8)
__AMDGCN_CLC_SUBGROUP_DOWN_TO_VEC(half16, DF16_, 16)
__AMDGCN_CLC_SUBGROUP_DOWN_TO_VEC(half2, Dh, 2)
__AMDGCN_CLC_SUBGROUP_DOWN_TO_VEC(half4, Dh, 4)
__AMDGCN_CLC_SUBGROUP_DOWN_TO_VEC(half8, Dh, 8)
__AMDGCN_CLC_SUBGROUP_DOWN_TO_VEC(half16, Dh, 16)
#endif // cl_khr_fp16
// float
__AMDGCN_CLC_SUBGROUP_DOWN_TO_VEC(float2, f, 2)
Expand Down
1 change: 0 additions & 1 deletion libclc/libspirv/lib/generic/SOURCES
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,6 @@ atomic/loadstore_helpers_unordered.ll
atomic/loadstore_helpers_release.ll
atomic/loadstore_helpers_acquire.ll
atomic/loadstore_helpers_seq_cst.ll
float16.cl
subnormal_config.cl
subnormal_helper_func.ll
async/async_work_group_strided_copy.cl
Expand Down
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