@@ -4416,24 +4416,28 @@ SPIRVValue *LLVMToSPIRVBase::transIntrinsicInst(IntrinsicInst *II,
44164416 BM->addIntegerType (VecTy->getElementType ()->getIntegerBitWidth ());
44174417 SPIRVTypeInt *I32STy = BM->addIntegerType (32 );
44184418 unsigned VecSize = VecTy->getElementCount ().getFixedValue ();
4419- SmallVector<SPIRVValue *, 16 > Extracts (VecSize);
4420- for (unsigned Idx = 0 ; Idx < VecSize; ++Idx) {
4421- Extracts[Idx] = BM->addVectorExtractDynamicInst (
4422- VecSVal, BM->addIntegerConstant (I32STy, Idx), BB);
4423- }
4424- unsigned Counter = VecSize >> 1 ;
4425- while (Counter != 0 ) {
4426- for (unsigned Idx = 0 ; Idx < Counter; ++Idx) {
4427- Extracts[Idx] = BM->addBinaryInst (Op, ResultSType, Extracts[Idx << 1 ],
4428- Extracts[(Idx << 1 ) + 1 ], BB);
4419+ if (VecSize > 0 ) {
4420+ SmallVector<SPIRVValue *, 16 > Extracts (VecSize);
4421+ for (unsigned Idx = 0 ; Idx < VecSize; ++Idx) {
4422+ Extracts[Idx] = BM->addVectorExtractDynamicInst (
4423+ VecSVal, BM->addIntegerConstant (I32STy, Idx), BB);
44294424 }
4430- Counter >>= 1 ;
4431- }
4432- if ((VecSize & 1 ) != 0 ) {
4433- Extracts[0 ] = BM->addBinaryInst (Op, ResultSType, Extracts[0 ],
4434- Extracts[VecSize - 1 ], BB);
4425+ unsigned Counter = VecSize >> 1 ;
4426+ while (Counter != 0 ) {
4427+ for (unsigned Idx = 0 ; Idx < Counter; ++Idx) {
4428+ Extracts[Idx] = BM->addBinaryInst (Op, ResultSType, Extracts[Idx << 1 ],
4429+ Extracts[(Idx << 1 ) + 1 ], BB);
4430+ }
4431+ Counter >>= 1 ;
4432+ }
4433+ if ((VecSize & 1 ) != 0 ) {
4434+ Extracts[0 ] = BM->addBinaryInst (Op, ResultSType, Extracts[0 ],
4435+ Extracts[VecSize - 1 ], BB);
4436+ }
4437+ return Extracts[0 ];
44354438 }
4436- return Extracts[0 ];
4439+ assert (VecSize && " Zero Extracts size for vector reduce lowering" );
4440+ return nullptr ;
44374441 }
44384442 case Intrinsic::vector_reduce_fadd:
44394443 case Intrinsic::vector_reduce_fmul: {
@@ -4492,27 +4496,31 @@ SPIRVValue *LLVMToSPIRVBase::transIntrinsicInst(IntrinsicInst *II,
44924496 SPIRVTypeInt *I32STy = BM->addIntegerType (32 );
44934497 unsigned VecSize = VecTy->getElementCount ().getFixedValue ();
44944498 SmallVector<SPIRVValue *, 16 > Extracts (VecSize);
4495- for (unsigned Idx = 0 ; Idx < VecSize; ++Idx) {
4496- Extracts[Idx] = BM->addVectorExtractDynamicInst (
4497- VecSVal, BM->addIntegerConstant (I32STy, Idx), BB);
4498- }
4499- unsigned Counter = VecSize >> 1 ;
4500- while (Counter != 0 ) {
4501- for (unsigned Idx = 0 ; Idx < Counter; ++Idx) {
4502- SPIRVValue *Cond = BM->addBinaryInst (Op, BoolSTy, Extracts[Idx << 1 ],
4503- Extracts[(Idx << 1 ) + 1 ], BB);
4504- Extracts[Idx] = BM->addSelectInst (Cond, Extracts[Idx << 1 ],
4505- Extracts[(Idx << 1 ) + 1 ], BB);
4499+ if (VecSize > 0 ) {
4500+ for (unsigned Idx = 0 ; Idx < VecSize; ++Idx) {
4501+ Extracts[Idx] = BM->addVectorExtractDynamicInst (
4502+ VecSVal, BM->addIntegerConstant (I32STy, Idx), BB);
45064503 }
4507- Counter >>= 1 ;
4508- }
4509- if ((VecSize & 1 ) != 0 ) {
4510- SPIRVValue *Cond = BM->addBinaryInst (Op, BoolSTy, Extracts[0 ],
4511- Extracts[VecSize - 1 ], BB);
4512- Extracts[0 ] =
4513- BM->addSelectInst (Cond, Extracts[0 ], Extracts[VecSize - 1 ], BB);
4504+ unsigned Counter = VecSize >> 1 ;
4505+ while (Counter != 0 ) {
4506+ for (unsigned Idx = 0 ; Idx < Counter; ++Idx) {
4507+ SPIRVValue *Cond = BM->addBinaryInst (Op, BoolSTy, Extracts[Idx << 1 ],
4508+ Extracts[(Idx << 1 ) + 1 ], BB);
4509+ Extracts[Idx] = BM->addSelectInst (Cond, Extracts[Idx << 1 ],
4510+ Extracts[(Idx << 1 ) + 1 ], BB);
4511+ }
4512+ Counter >>= 1 ;
4513+ }
4514+ if ((VecSize & 1 ) != 0 ) {
4515+ SPIRVValue *Cond = BM->addBinaryInst (Op, BoolSTy, Extracts[0 ],
4516+ Extracts[VecSize - 1 ], BB);
4517+ Extracts[0 ] =
4518+ BM->addSelectInst (Cond, Extracts[0 ], Extracts[VecSize - 1 ], BB);
4519+ }
4520+ return Extracts[0 ];
45144521 }
4515- return Extracts[0 ];
4522+ assert (VecSize && " Zero Extracts size for vector reduce lowering" );
4523+ return nullptr ;
45164524 }
45174525 case Intrinsic::memset: {
45184526 // Generally there is no direct mapping of memset to SPIR-V. But it turns
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