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  1. If blocking, read valid reg, wait until valid is 0.
  2. If non-blocking, read valid reg once ->return failure if valid is 1.
  3. write to the pipe.
  4. write 1 to the valid.

@zibaiwan zibaiwan requested a review from sophimao November 27, 2023 16:52
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sophimao previously approved these changes Nov 27, 2023
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Thanks Zibai! LGTM except for a minor nit on comment.

1. If blocking, read valid reg, wait until valid is 0.
2. If non-blocking, read valid reg once ->return failure if valid is 1.
3. write to the pipe.
4. write 1 to the valid.
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Thanks Zibai!

@zibaiwan zibaiwan merged commit 78dd354 into intel:main Dec 1, 2023
@zibaiwan zibaiwan deleted the fix-csr branch December 1, 2023 15:01
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2 participants