FPGA with Xilinx Vitis HLS 2020.2

-1- FPGA Tutorial with HLS

Undergraduate internship Dec. 2020 ~ Feb. 2021
Accelerated Computing Systems Lab affiliated with CS, Yonsei University, South Korea.
Device: xc7z020clg484-1

Lab05 Hello World with Vitis and Vivado
Lab06 Working with HLS
Lab08 Matrix Multiplier Design
Lab08 Matrix Multiplier Design Source Files
Troubleshootings

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(Next) -2- FPGA AXI and VHDL

https://github.com/hajin-kim/FPGA_AXI_and_VHDL

(Next) -3- FPGA Tiny CPU

https://github.com/hajin-kim/FPGA_Tiny_CPU