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Add dont_touches + Basic Floorplan for DRAM controllers #40
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This mostly looks fine, I'd just like to clarify why the tck to real clocks aren't being made into async clock groups anymore. The commented out contstraints are maybe something we could clean up before adding them into the repo but I'll leave that to you to decide.
# False paths between main clock and tck | ||
set_clock_groups -name TIG_SRAI_1 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]] | ||
set_clock_groups -name TIG_SRAI_2 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck] | ||
set_clock_groups -name TIG_SRAI_3 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]] |
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@davidbiancolin are these being removed intentionally? If so, could you explain why they aren't needed?
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David is following up with AWS in https://forums.aws.amazon.com/thread.jspa?threadID=342848&tstart=0
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AWS has confirmed we can remove this (see the forum post above).
This PR does two things:
I pulled in the floorplan from cl_dram_dma, and just kept the pblock constraints for nodes that are common across that example design and our design. I think we could consider pulling in some of the DRAM crossbar, but i'll leave that to a later PR.