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feat(uart): [IDF 5.3] fixes HardwareSerial::updateBaudRate() using a baud rate higher 230400 - checks UART Clock Source #10643

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Merged
merged 2 commits into from
Nov 25, 2024
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feat(uart): [IDF 5.3] fixes HardwareSerial::updateBaudRate() using a baud rate higher 230400 - checks UART Clock Source #10643

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4f46d27
fix(uart): fixes issue with update baudrate higher than 250000
SuGlider Nov 23, 2024
e4fd823
ci(pre-commit): Apply automatic fixes
pre-commit-ci-lite[bot] Nov 25, 2024
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9 changes: 7 additions & 2 deletions cores/esp32/esp32-hal-uart.c
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Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,8 @@
#include "hal/gpio_hal.h"
#include "esp_rom_gpio.h"

static int s_uart_debug_nr = 0; // UART number for debug output
static int s_uart_debug_nr = 0; // UART number for debug output
#define REF_TICK_BAUDRATE_LIMIT 250000 // this is maximum UART badrate using REF_TICK as clock

struct uart_struct_t {

Expand Down Expand Up @@ -522,7 +523,7 @@ uart_t *uartBegin(
#if SOC_UART_SUPPORT_XTAL_CLK
uart_config.source_clk = UART_SCLK_XTAL; // valid for C2, S3, C3, C6, H2 and P4
#elif SOC_UART_SUPPORT_REF_TICK
if (baudrate <= 250000) {
if (baudrate <= REF_TICK_BAUDRATE_LIMIT) {
uart_config.source_clk = UART_SCLK_REF_TICK; // valid for ESP32, S2 - MAX supported baud rate is 250 Kbps
} else {
uart_config.source_clk = UART_SCLK_APB; // baudrate may change with the APB Frequency!
Expand Down Expand Up @@ -804,6 +805,10 @@ void uartSetBaudRate(uart_t *uart, uint32_t baud_rate) {
return;
}
UART_MUTEX_LOCK();
#if !SOC_UART_SUPPORT_XTAL_CLK
soc_module_clk_t newClkSrc = baud_rate <= REF_TICK_BAUDRATE_LIMIT ? SOC_MOD_CLK_REF_TICK : SOC_MOD_CLK_APB;
uart_ll_set_sclk(UART_LL_GET_HW(uart->num), newClkSrc);
#endif
if (uart_set_baudrate(uart->num, baud_rate) == ESP_OK) {
uart->_baudrate = baud_rate;
} else {
Expand Down
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