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Assertion failed 'varDsc->lvLiveInOutOfHndlr || ((regSet.GetMaskVars() & regMask) == 0) #52945

@kunalspathak

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@kunalspathak

Hitting the assert in libraries jitstressregs since last month. I spent some time bisecting the change that caused it, but for some reason, I was hitting it for every commit of last month.

Here is a superpmi repro:

D:\git\runtime\src\coreclr\jit>%CORE_ROOT%\superpmi.exe -c 2830 %CORE_ROOT%\clrjit_unix_arm_x86.dll E:\spmi\mch\529be99f-ce88-426e-a099-7528a691226c.Linux.arm\libraries.pmi.Linux.arm.checked.mch
Using jit(D:\git\runtime\artifacts\tests\coreclr\windows.x86.Checked\tests\Core_Root\clrjit_unix_arm_x86.dll) with input (E:\spmi\mch\529be99f-ce88-426e-a099-7528a691226c.Linux.arm\libraries.pmi.Linux.arm.checked.mch)
 indexCount=1 (2830)
Jit startup took 12.882500ms
ISSUE: <ASSERT> D:\git\runtime\src\coreclr\jit\codegencommon.cpp (487) - Assertion failed 'varDsc->lvLiveInOutOfHndlr || ((regSet.GetMaskVars() & regMask) == 0)' in 'Microsoft.VisualBasic.CompilerServices.VBBinder:BindToMethod(int,System.Reflection.MethodBase[],byref,System.Reflection.ParameterModifier[],System.Globalization.CultureInfo,System.String[],byref):System.Reflection.MethodBase:this' during 'Generate code' (IL size 4649)

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arch-arm32area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI

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