Remove the `AddScaleSU` performance regression for AVX

[adamsitnik]

Our profiles show that AddScaleSU which should be faster with AVX is actually slower and takes more time. This can be confirmed running our CpuMathBenchmarks:

..\..\Tools\dotnetcli\dotnet.exe run -c Release-Intrinsics -- -f *.AddScaleSU --join

Type	Method	Mean
AvxPerformanceTests	AddScaleSU	4.012 ms
NativePerformanceTests	AddScaleSU	2.966 ms
SsePerformanceTests	AddScaleSU	2.916 ms

This issue has been spotted by @eerhardt in August #691 (comment)

@helloguo suggested #691 (comment) that GatherVector256 intrinsic should be used

[eerhardt]

GatherVector256 is now implemented: dotnet/coreclr#19392, so we should be able to use the latest .NET Core 3.0 runtime and we should be able to fix this.

[helloguo]

I can update the code with GatherVector256. Please assign it to me :)

[adamsitnik]

@helloguo GitHub won't let me actually set the assigned to field to you, but this note indicates that others should not work on it without interacting here.

@eerhardt if you have the rights to assign @helloguo to this issue please do so

[eerhardt]

I can't either - I think it is because @helloguo is not a contributor to this repo...?

[adamsitnik]

I have to reopen this issue, #1200 has helped a LOT, but it's still slower:

BenchmarkDotNet=v0.11.1.786-nightly, OS=Windows 10.0.17134.285 (1803/April2018Update/Redstone4)
Intel Xeon CPU E5-1650 v4 3.60GHz, 1 CPU, 12 logical and 6 physical cores
Frequency=3507500 Hz, Resolution=285.1033 ns, Timer=TSC
.NET Core SDK=3.0.100-alpha1-009642
  [Host] : .NET Core 3.0.0-preview1-27004-04 (CoreCLR 4.6.27003.04, CoreFX 4.6.27003.02), 64bit RyuJIT

Job=ShortRun  Toolchain=InProcessToolchain  IterationCount=3  
LaunchCount=3  WarmupCount=3  

Type	Method	Mean	Error	StdDev
AvxPerformanceTests	AddScaleSU	3.501 ms	0.1372 ms	0.0817 ms
NativePerformanceTests	AddScaleSU	2.762 ms	0.0464 ms	0.0276 ms
SsePerformanceTests	AddScaleSU	2.862 ms	0.0679 ms	0.0404 ms

[danmoseley]

BTW, would any other methods in avxintrinsics.cs potentially benefit from an AVX2 codepath? If so we should open an up for grabs issue. @tannergooding

[tannergooding]

@adamsitnik, @helloguo. Is the perf differences potentially caused by the varying latency per microarchitecture for the VGATHER* instructions?

Agner's Instruction Tables gives the following (see https://www.agner.org/optimize/instruction_tables.pdf for more details):

AMD Ryzen

Instruction	Operands	Ops	Reciprocal throughput	Execution pipes	Domain, notes
VGATHERDPS	x,[r+s*x],x	38	13	P0 P1 P2	AVX2
VGATHERDPS	y,[r+s*y],y	66	20	P0 P1 P2	AVX2
VGATHERQPS	x,[r+s*x],x	24	9	P0 P1 P2	AVX2
VGATHERQPS	x,[r+s*y],x	36	12	P0 P1 P2	AVX2
VGATHERDPD	x,[r+s*x],x	23	9	P0 P1 P2	AVX2
VGATHERDPD	y,[r+s*x],y	35	12	P0 P1 P2	AVX2
VGATHERQPD	x,[r+s*x],x	23	9	P0 P1 P2	AVX2
VGATHERQPD	y,[r+s*y],y	35	12	P0 P1 P2	AVX2

Intel Haswell

Instruction	Operands	uops fused domain	uops unfused domain	throughput	comments
VGATHERDPS	x,[r+s*x],x	20	20	9	AVX2
VGATHERDPS	y,[r+s*y],y	34	34	12	AVX2
VGATHERQPS	x,[r+s*x],x	15	15	8	AVX2
VGATHERQPS	x,[r+s*y],x	22	22	7	AVX2
VGATHERDPD	x,[r+s*x],x	12	12	7	AVX2
VGATHERDPD	y,[r+s*x],y	20	20	9	AVX2
VGATHERQPD	x,[r+s*x],x	14	14	7	AVX2
VGATHERQPD	y,[r+s*y],y	22	22	9	AVX2

Intel Broadwell

Instruction	Operands	uops fused domain	uops unfused domain	throughput	comments
VGATHERDPS	x,[r+s*x],x	10	10	6	AVX2
VGATHERDPS	y,[r+s*y],y	14	14	7	AVX2
VGATHERQPS	x,[r+s*x],x	9	9	6	AVX2
VGATHERQPS	x,[r+s*y],x	10	10	6	AVX2
VGATHERDPD	x,[r+s*x],x	7	7	5	AVX2
VGATHERDPD	y,[r+s*x],y	9	9	6	AVX2
VGATHERQPD	x,[r+s*x],x	7	7	5	AVX2
VGATHERQPD	y,[r+s*y],y	9	9	6	AVX2

Intel Skylake

Instruction	Operands	uops fused domain	uops unfused domain	uops each port	Latency	throughput	comments
VGATHERDPS	x,[r+s*x],x	4	4	p0 p1 p23 p5	12	4	AVX2
VGATHERDPS	y,[r+s*y],y	4	4	p0 p1 p23 p5	13	5	AVX2
VGATHERQPS	x,[r+s*x],x	5	5	p0 p1 p23 p5		2	AVX2
VGATHERQPS	x,[r+s*y],x	4	4	p0 p1 p23 p5		4	AVX2
VGATHERDPD	x,[r+s*x],x	5	5	p0 p1 p23 p5		2	AVX2
VGATHERDPD	y,[r+s*x],y	4	4	p0 p1 p23 p5		4	AVX2
VGATHERQPD	x,[r+s*x],x	5	5	p0 p1 p23 p5		2	AVX2
VGATHERQPD	y,[r+s*y],y	4	4	p0 p1 p23 p5		4	AVX2