SystemVerilog: conversion functions #894
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tautschnig
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Jan 3, 2025
| // Not a conversion, just reinterpretation | ||
| always assert ($bitstoreal(0)==0.0); | ||
| always assert ($bitstoreal('h3ff00000_00000000)==1); | ||
| // always assert ($bitstoreal('hc0000000_00000000)==-2.0); |
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| // always assert ($bitstoreal('hc0000000_00000000)==-2.0); | |
| // always assert ($bitstoreal('hc0000000_00000000)==-2.0); |
| // Not a conversion, just reinterpretation | ||
| always assert ($bitstoshortreal(0)==0.0); | ||
| always assert ($bitstoshortreal('h3f80_0000)==1.0); | ||
| // always assert ($bitstoshortreal('hc000_0000)==-2.0); |
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| // always assert ($bitstoshortreal('hc000_0000)==-2.0); | |
| // always assert ($bitstoshortreal('hc000_0000)==-2.0); |
src/verilog/verilog_lowering.cpp
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| { | ||
| // lower to typecast | ||
| DATA_INVARIANT( | ||
| arguments.size() == 1, id2string(identifier) + " must have one argument"); |
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| arguments.size() == 1, id2string(identifier) + " must have one argument"); | |
| arguments.size() == 1, id2string(identifier) + " takes one argument"); |
for consistency with the other cases.
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This adds the conversion functions from 1800-2017 20.5.
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This adds the conversion functions from 1800-2017 20.5.