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Verilog: KNOWNBUG test for module port with value #1254

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Verilog: KNOWNBUG test for module port with value #1254

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9 changes: 9 additions & 0 deletions regression/verilog/modules/port_with_value1.desc
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Original file line number Diff line number Diff line change
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KNOWNBUG
port_with_value1.sv

^EXIT=0$
^SIGNAL=0$
--
^warning: ignoring
--
This yields a syntax error.
14 changes: 14 additions & 0 deletions regression/verilog/modules/port_with_value1.sv
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Original file line number Diff line number Diff line change
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module M1(input [31:0] in1 = 1234, in2 = 4567);

assert final (in1 == in2);

endmodule

module main;
// inputs not connected
M1 m1();

// in2 connected
M1 m2(.in2(1234));

endmodule
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