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net: hns3: handle hw errors of SSU
This patch enables and handles hw errors of the Storage Switch Unit(SSU). Signed-off-by: Shiju Jose <[email protected]> Signed-off-by: Salil Mehta <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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‎drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -217,6 +217,8 @@ enum hclge_opcode_type {
217217
/* Error INT commands */
218218
HCLGE_MAC_COMMON_INT_EN = 0x030E,
219219
HCLGE_TM_SCH_ECC_INT_EN = 0x0829,
220+
HCLGE_SSU_ECC_INT_CMD = 0x0989,
221+
HCLGE_SSU_COMMON_INT_CMD = 0x098C,
220222
HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40,
221223
HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41,
222224
HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42,

‎drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c‎

Lines changed: 187 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -263,6 +263,80 @@ static const struct hclge_hw_error hclge_ppu_pf_abnormal_int[] = {
263263
{ /* sentinel */ }
264264
};
265265

266+
static const struct hclge_hw_error hclge_ssu_com_err_int[] = {
267+
{ .int_msk = BIT(0), .msg = "buf_sum_err" },
268+
{ .int_msk = BIT(1), .msg = "ppp_mb_num_err" },
269+
{ .int_msk = BIT(2), .msg = "ppp_mbid_err" },
270+
{ .int_msk = BIT(3), .msg = "ppp_rlt_mac_err" },
271+
{ .int_msk = BIT(4), .msg = "ppp_rlt_host_err" },
272+
{ .int_msk = BIT(5), .msg = "cks_edit_position_err" },
273+
{ .int_msk = BIT(6), .msg = "cks_edit_condition_err" },
274+
{ .int_msk = BIT(7), .msg = "vlan_edit_condition_err" },
275+
{ .int_msk = BIT(8), .msg = "vlan_num_ot_err" },
276+
{ .int_msk = BIT(9), .msg = "vlan_num_in_err" },
277+
{ /* sentinel */ }
278+
};
279+
280+
static const struct hclge_hw_error hclge_ssu_port_based_err_int[] = {
281+
{ .int_msk = BIT(0), .msg = "roc_pkt_without_key_port" },
282+
{ .int_msk = BIT(1), .msg = "tpu_pkt_without_key_port" },
283+
{ .int_msk = BIT(2), .msg = "igu_pkt_without_key_port" },
284+
{ .int_msk = BIT(3), .msg = "roc_eof_mis_match_port" },
285+
{ .int_msk = BIT(4), .msg = "tpu_eof_mis_match_port" },
286+
{ .int_msk = BIT(5), .msg = "igu_eof_mis_match_port" },
287+
{ .int_msk = BIT(6), .msg = "roc_sof_mis_match_port" },
288+
{ .int_msk = BIT(7), .msg = "tpu_sof_mis_match_port" },
289+
{ .int_msk = BIT(8), .msg = "igu_sof_mis_match_port" },
290+
{ .int_msk = BIT(11), .msg = "ets_rd_int_rx_port" },
291+
{ .int_msk = BIT(12), .msg = "ets_wr_int_rx_port" },
292+
{ .int_msk = BIT(13), .msg = "ets_rd_int_tx_port" },
293+
{ .int_msk = BIT(14), .msg = "ets_wr_int_tx_port" },
294+
{ /* sentinel */ }
295+
};
296+
297+
static const struct hclge_hw_error hclge_ssu_fifo_overflow_int[] = {
298+
{ .int_msk = BIT(0), .msg = "ig_mac_inf_int" },
299+
{ .int_msk = BIT(1), .msg = "ig_host_inf_int" },
300+
{ .int_msk = BIT(2), .msg = "ig_roc_buf_int" },
301+
{ .int_msk = BIT(3), .msg = "ig_host_data_fifo_int" },
302+
{ .int_msk = BIT(4), .msg = "ig_host_key_fifo_int" },
303+
{ .int_msk = BIT(5), .msg = "tx_qcn_fifo_int" },
304+
{ .int_msk = BIT(6), .msg = "rx_qcn_fifo_int" },
305+
{ .int_msk = BIT(7), .msg = "tx_pf_rd_fifo_int" },
306+
{ .int_msk = BIT(8), .msg = "rx_pf_rd_fifo_int" },
307+
{ .int_msk = BIT(9), .msg = "qm_eof_fifo_int" },
308+
{ .int_msk = BIT(10), .msg = "mb_rlt_fifo_int" },
309+
{ .int_msk = BIT(11), .msg = "dup_uncopy_fifo_int" },
310+
{ .int_msk = BIT(12), .msg = "dup_cnt_rd_fifo_int" },
311+
{ .int_msk = BIT(13), .msg = "dup_cnt_drop_fifo_int" },
312+
{ .int_msk = BIT(14), .msg = "dup_cnt_wrb_fifo_int" },
313+
{ .int_msk = BIT(15), .msg = "host_cmd_fifo_int" },
314+
{ .int_msk = BIT(16), .msg = "mac_cmd_fifo_int" },
315+
{ .int_msk = BIT(17), .msg = "host_cmd_bitmap_empty_int" },
316+
{ .int_msk = BIT(18), .msg = "mac_cmd_bitmap_empty_int" },
317+
{ .int_msk = BIT(19), .msg = "dup_bitmap_empty_int" },
318+
{ .int_msk = BIT(20), .msg = "out_queue_bitmap_empty_int" },
319+
{ .int_msk = BIT(21), .msg = "bank2_bitmap_empty_int" },
320+
{ .int_msk = BIT(22), .msg = "bank1_bitmap_empty_int" },
321+
{ .int_msk = BIT(23), .msg = "bank0_bitmap_empty_int" },
322+
{ /* sentinel */ }
323+
};
324+
325+
static const struct hclge_hw_error hclge_ssu_ets_tcg_int[] = {
326+
{ .int_msk = BIT(0), .msg = "ets_rd_int_rx_tcg" },
327+
{ .int_msk = BIT(1), .msg = "ets_wr_int_rx_tcg" },
328+
{ .int_msk = BIT(2), .msg = "ets_rd_int_tx_tcg" },
329+
{ .int_msk = BIT(3), .msg = "ets_wr_int_tx_tcg" },
330+
{ /* sentinel */ }
331+
};
332+
333+
static const struct hclge_hw_error hclge_ssu_port_based_pf_int[] = {
334+
{ .int_msk = BIT(0), .msg = "roc_pkt_without_key_port" },
335+
{ .int_msk = BIT(9), .msg = "low_water_line_err_port" },
336+
{ .int_msk = BIT(10), .msg = "hi_water_line_err_port" },
337+
{ /* sentinel */ }
338+
};
339+
266340
static void hclge_log_error(struct device *dev, char *reg,
267341
const struct hclge_hw_error *err,
268342
u32 err_sts)
@@ -606,6 +680,63 @@ static int hclge_config_ppu_hw_err_int(struct hclge_dev *hdev, bool en)
606680
return ret;
607681
}
608682

683+
static int hclge_config_ssu_hw_err_int(struct hclge_dev *hdev, bool en)
684+
{
685+
struct device *dev = &hdev->pdev->dev;
686+
struct hclge_desc desc[2];
687+
int ret;
688+
689+
/* configure SSU ecc error interrupts */
690+
hclge_cmd_setup_basic_desc(&desc[0], HCLGE_SSU_ECC_INT_CMD, false);
691+
desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
692+
hclge_cmd_setup_basic_desc(&desc[1], HCLGE_SSU_ECC_INT_CMD, false);
693+
if (en) {
694+
desc[0].data[0] = cpu_to_le32(HCLGE_SSU_1BIT_ECC_ERR_INT_EN);
695+
desc[0].data[1] =
696+
cpu_to_le32(HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN);
697+
desc[0].data[4] = cpu_to_le32(HCLGE_SSU_BIT32_ECC_ERR_INT_EN);
698+
}
699+
700+
desc[1].data[0] = cpu_to_le32(HCLGE_SSU_1BIT_ECC_ERR_INT_EN_MASK);
701+
desc[1].data[1] = cpu_to_le32(HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK);
702+
desc[1].data[2] = cpu_to_le32(HCLGE_SSU_BIT32_ECC_ERR_INT_EN_MASK);
703+
704+
ret = hclge_cmd_send(&hdev->hw, &desc[0], 2);
705+
if (ret) {
706+
dev_err(dev,
707+
"fail(%d) to configure SSU ECC error interrupt\n", ret);
708+
return ret;
709+
}
710+
711+
/* configure SSU common error interrupts */
712+
hclge_cmd_setup_basic_desc(&desc[0], HCLGE_SSU_COMMON_INT_CMD, false);
713+
desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
714+
hclge_cmd_setup_basic_desc(&desc[1], HCLGE_SSU_COMMON_INT_CMD, false);
715+
716+
if (en) {
717+
if (hdev->pdev->revision >= 0x21)
718+
desc[0].data[0] =
719+
cpu_to_le32(HCLGE_SSU_COMMON_INT_EN);
720+
else
721+
desc[0].data[0] =
722+
cpu_to_le32(HCLGE_SSU_COMMON_INT_EN & ~BIT(5));
723+
desc[0].data[1] = cpu_to_le32(HCLGE_SSU_PORT_BASED_ERR_INT_EN);
724+
desc[0].data[2] =
725+
cpu_to_le32(HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN);
726+
}
727+
728+
desc[1].data[0] = cpu_to_le32(HCLGE_SSU_COMMON_INT_EN_MASK |
729+
HCLGE_SSU_PORT_BASED_ERR_INT_EN_MASK);
730+
desc[1].data[1] = cpu_to_le32(HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK);
731+
732+
ret = hclge_cmd_send(&hdev->hw, &desc[0], 2);
733+
if (ret)
734+
dev_err(dev,
735+
"fail(%d) to configure SSU COMMON error intr\n", ret);
736+
737+
return ret;
738+
}
739+
609740
#define HCLGE_SET_DEFAULT_RESET_REQUEST(reset_type) \
610741
do { \
611742
if (ae_dev->ops->set_default_reset_request) \
@@ -676,6 +807,27 @@ static int hclge_handle_mpf_ras_error(struct hclge_dev *hdev,
676807
HCLGE_SET_DEFAULT_RESET_REQUEST(HNAE3_CORE_RESET);
677808
}
678809

810+
/* log SSU(Storage Switch Unit) errors */
811+
desc_data = (__le32 *)&desc[2];
812+
status = le32_to_cpu(*(desc_data + 2));
813+
if (status) {
814+
dev_warn(dev, "SSU_ECC_MULTI_BIT_INT_0 ssu_ecc_mbit_int[31:0]\n");
815+
HCLGE_SET_DEFAULT_RESET_REQUEST(HNAE3_CORE_RESET);
816+
}
817+
818+
status = le32_to_cpu(*(desc_data + 3)) & BIT(0);
819+
if (status) {
820+
dev_warn(dev, "SSU_ECC_MULTI_BIT_INT_1 ssu_ecc_mbit_int[32]\n");
821+
HCLGE_SET_DEFAULT_RESET_REQUEST(HNAE3_CORE_RESET);
822+
}
823+
824+
status = le32_to_cpu(*(desc_data + 4)) & HCLGE_SSU_COMMON_ERR_INT_MASK;
825+
if (status) {
826+
hclge_log_error(dev, "SSU_COMMON_ERR_INT",
827+
&hclge_ssu_com_err_int[0], status);
828+
HCLGE_SET_DEFAULT_RESET_REQUEST(HNAE3_GLOBAL_RESET);
829+
}
830+
679831
/* log IGU(Ingress Unit) errors */
680832
desc_data = (__le32 *)&desc[3];
681833
status = le32_to_cpu(*desc_data) & HCLGE_IGU_INT_MASK;
@@ -775,6 +927,7 @@ static int hclge_handle_pf_ras_error(struct hclge_dev *hdev,
775927
struct hclge_desc *desc,
776928
int num)
777929
{
930+
struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
778931
struct device *dev = &hdev->pdev->dev;
779932
__le32 *desc_data;
780933
u32 status;
@@ -791,6 +944,28 @@ static int hclge_handle_pf_ras_error(struct hclge_dev *hdev,
791944
return ret;
792945
}
793946

947+
/* log SSU(Storage Switch Unit) errors */
948+
status = le32_to_cpu(desc[0].data[0]);
949+
if (status) {
950+
hclge_log_error(dev, "SSU_PORT_BASED_ERR_INT",
951+
&hclge_ssu_port_based_err_int[0], status);
952+
HCLGE_SET_DEFAULT_RESET_REQUEST(HNAE3_GLOBAL_RESET);
953+
}
954+
955+
status = le32_to_cpu(desc[0].data[1]);
956+
if (status) {
957+
hclge_log_error(dev, "SSU_FIFO_OVERFLOW_INT",
958+
&hclge_ssu_fifo_overflow_int[0], status);
959+
HCLGE_SET_DEFAULT_RESET_REQUEST(HNAE3_GLOBAL_RESET);
960+
}
961+
962+
status = le32_to_cpu(desc[0].data[2]);
963+
if (status) {
964+
hclge_log_error(dev, "SSU_ETS_TCG_INT",
965+
&hclge_ssu_ets_tcg_int[0], status);
966+
HCLGE_SET_DEFAULT_RESET_REQUEST(HNAE3_GLOBAL_RESET);
967+
}
968+
794969
/* log IGU(Ingress Unit) EGU(Egress Unit) TNL errors */
795970
desc_data = (__le32 *)&desc[1];
796971
status = le32_to_cpu(*desc_data) & HCLGE_IGU_EGU_TNL_INT_MASK;
@@ -857,6 +1032,10 @@ static const struct hclge_hw_blk hw_blk[] = {
8571032
.msk = BIT(1), .name = "PPP",
8581033
.config_err_int = hclge_config_ppp_hw_err_int,
8591034
},
1035+
{
1036+
.msk = BIT(2), .name = "SSU",
1037+
.config_err_int = hclge_config_ssu_hw_err_int,
1038+
},
8601039
{
8611040
.msk = BIT(3), .name = "PPU",
8621041
.config_err_int = hclge_config_ppu_hw_err_int,
@@ -1009,6 +1188,14 @@ int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
10091188
goto msi_error;
10101189
}
10111190

1191+
/* log SSU PF errors */
1192+
status = le32_to_cpu(desc[0].data[0]) & HCLGE_SSU_PORT_INT_MSIX_MASK;
1193+
if (status) {
1194+
hclge_log_error(dev, "SSU_PORT_BASED_ERR_INT",
1195+
&hclge_ssu_port_based_pf_int[0], status);
1196+
set_bit(HNAE3_GLOBAL_RESET, reset_requests);
1197+
}
1198+
10121199
/* read and log PPP PF errors */
10131200
desc_data = (__le32 *)&desc[2];
10141201
status = le32_to_cpu(*desc_data);

‎drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,21 @@
5858
#define HCLGE_PPU_MPF_ABNORMAL_INT3_EN_MASK GENMASK(23, 16)
5959
#define HCLGE_PPU_PF_ABNORMAL_INT_EN GENMASK(5, 0)
6060
#define HCLGE_PPU_PF_ABNORMAL_INT_EN_MASK GENMASK(5, 0)
61+
#define HCLGE_SSU_1BIT_ECC_ERR_INT_EN GENMASK(31, 0)
62+
#define HCLGE_SSU_1BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
63+
#define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN GENMASK(31, 0)
64+
#define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
65+
#define HCLGE_SSU_BIT32_ECC_ERR_INT_EN 0x0101
66+
#define HCLGE_SSU_BIT32_ECC_ERR_INT_EN_MASK 0x0101
67+
#define HCLGE_SSU_COMMON_INT_EN GENMASK(9, 0)
68+
#define HCLGE_SSU_COMMON_INT_EN_MASK GENMASK(9, 0)
69+
#define HCLGE_SSU_PORT_BASED_ERR_INT_EN 0x0BFF
70+
#define HCLGE_SSU_PORT_BASED_ERR_INT_EN_MASK 0x0BFF0000
71+
#define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN GENMASK(23, 0)
72+
#define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK GENMASK(23, 0)
6173

74+
#define HCLGE_SSU_COMMON_ERR_INT_MASK GENMASK(9, 0)
75+
#define HCLGE_SSU_PORT_INT_MSIX_MASK 0x7BFF
6276
#define HCLGE_IGU_INT_MASK GENMASK(3, 0)
6377
#define HCLGE_IGU_EGU_TNL_INT_MASK GENMASK(5, 0)
6478
#define HCLGE_PPP_MPF_INT_ST3_MASK GENMASK(5, 0)

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