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shijujose4davem330
shijujose4
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davem330
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net: hns3: handle hw errors of PPU(RCB)
This patch enables and handles hw RAS and MSIx errors of PPU(RCB). Signed-off-by: Shiju Jose <[email protected]> Signed-off-by: Salil Mehta <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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‎drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -217,6 +217,9 @@ enum hclge_opcode_type {
217217
/* Error INT commands */
218218
HCLGE_MAC_COMMON_INT_EN = 0x030E,
219219
HCLGE_TM_SCH_ECC_INT_EN = 0x0829,
220+
HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40,
221+
HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41,
222+
HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42,
220223
HCLGE_COMMON_ECC_INT_CFG = 0x1505,
221224
HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510,
222225
HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511,

‎drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c‎

Lines changed: 162 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -222,6 +222,47 @@ static const struct hclge_hw_error hclge_mac_afifo_tnl_int[] = {
222222
{ /* sentinel */ }
223223
};
224224

225+
static const struct hclge_hw_error hclge_ppu_mpf_abnormal_int_st2[] = {
226+
{ .int_msk = BIT(13), .msg = "rpu_rx_pkt_bit32_ecc_mbit_err" },
227+
{ .int_msk = BIT(14), .msg = "rpu_rx_pkt_bit33_ecc_mbit_err" },
228+
{ .int_msk = BIT(15), .msg = "rpu_rx_pkt_bit34_ecc_mbit_err" },
229+
{ .int_msk = BIT(16), .msg = "rpu_rx_pkt_bit35_ecc_mbit_err" },
230+
{ .int_msk = BIT(17), .msg = "rcb_tx_ring_ecc_mbit_err" },
231+
{ .int_msk = BIT(18), .msg = "rcb_rx_ring_ecc_mbit_err" },
232+
{ .int_msk = BIT(19), .msg = "rcb_tx_fbd_ecc_mbit_err" },
233+
{ .int_msk = BIT(20), .msg = "rcb_rx_ebd_ecc_mbit_err" },
234+
{ .int_msk = BIT(21), .msg = "rcb_tso_info_ecc_mbit_err" },
235+
{ .int_msk = BIT(22), .msg = "rcb_tx_int_info_ecc_mbit_err" },
236+
{ .int_msk = BIT(23), .msg = "rcb_rx_int_info_ecc_mbit_err" },
237+
{ .int_msk = BIT(24), .msg = "tpu_tx_pkt_0_ecc_mbit_err" },
238+
{ .int_msk = BIT(25), .msg = "tpu_tx_pkt_1_ecc_mbit_err" },
239+
{ .int_msk = BIT(26), .msg = "rd_bus_err" },
240+
{ .int_msk = BIT(27), .msg = "wr_bus_err" },
241+
{ .int_msk = BIT(28), .msg = "reg_search_miss" },
242+
{ .int_msk = BIT(29), .msg = "rx_q_search_miss" },
243+
{ .int_msk = BIT(30), .msg = "ooo_ecc_err_detect" },
244+
{ .int_msk = BIT(31), .msg = "ooo_ecc_err_multpl" },
245+
{ /* sentinel */ }
246+
};
247+
248+
static const struct hclge_hw_error hclge_ppu_mpf_abnormal_int_st3[] = {
249+
{ .int_msk = BIT(4), .msg = "gro_bd_ecc_mbit_err" },
250+
{ .int_msk = BIT(5), .msg = "gro_context_ecc_mbit_err" },
251+
{ .int_msk = BIT(6), .msg = "rx_stash_cfg_ecc_mbit_err" },
252+
{ .int_msk = BIT(7), .msg = "axi_rd_fbd_ecc_mbit_err" },
253+
{ /* sentinel */ }
254+
};
255+
256+
static const struct hclge_hw_error hclge_ppu_pf_abnormal_int[] = {
257+
{ .int_msk = BIT(0), .msg = "over_8bd_no_fe" },
258+
{ .int_msk = BIT(1), .msg = "tso_mss_cmp_min_err" },
259+
{ .int_msk = BIT(2), .msg = "tso_mss_cmp_max_err" },
260+
{ .int_msk = BIT(3), .msg = "tx_rd_fbd_poison" },
261+
{ .int_msk = BIT(4), .msg = "rx_rd_ebd_poison" },
262+
{ .int_msk = BIT(5), .msg = "buf_wait_timeout" },
263+
{ /* sentinel */ }
264+
};
265+
225266
static void hclge_log_error(struct device *dev, char *reg,
226267
const struct hclge_hw_error *err,
227268
u32 err_sts)
@@ -489,6 +530,82 @@ static int hclge_config_mac_err_int(struct hclge_dev *hdev, bool en)
489530
return ret;
490531
}
491532

533+
static int hclge_config_ppu_error_interrupts(struct hclge_dev *hdev, u32 cmd,
534+
bool en)
535+
{
536+
struct device *dev = &hdev->pdev->dev;
537+
struct hclge_desc desc[2];
538+
int num = 1;
539+
int ret;
540+
541+
/* configure PPU error interrupts */
542+
if (cmd == HCLGE_PPU_MPF_ECC_INT_CMD) {
543+
hclge_cmd_setup_basic_desc(&desc[0], cmd, false);
544+
desc[0].flag |= HCLGE_CMD_FLAG_NEXT;
545+
hclge_cmd_setup_basic_desc(&desc[1], cmd, false);
546+
if (en) {
547+
desc[0].data[0] = HCLGE_PPU_MPF_ABNORMAL_INT0_EN;
548+
desc[0].data[1] = HCLGE_PPU_MPF_ABNORMAL_INT1_EN;
549+
desc[1].data[3] = HCLGE_PPU_MPF_ABNORMAL_INT3_EN;
550+
desc[1].data[4] = HCLGE_PPU_MPF_ABNORMAL_INT2_EN;
551+
}
552+
553+
desc[1].data[0] = HCLGE_PPU_MPF_ABNORMAL_INT0_EN_MASK;
554+
desc[1].data[1] = HCLGE_PPU_MPF_ABNORMAL_INT1_EN_MASK;
555+
desc[1].data[2] = HCLGE_PPU_MPF_ABNORMAL_INT2_EN_MASK;
556+
desc[1].data[3] |= HCLGE_PPU_MPF_ABNORMAL_INT3_EN_MASK;
557+
num = 2;
558+
} else if (cmd == HCLGE_PPU_MPF_OTHER_INT_CMD) {
559+
hclge_cmd_setup_basic_desc(&desc[0], cmd, false);
560+
if (en)
561+
desc[0].data[0] = HCLGE_PPU_MPF_ABNORMAL_INT2_EN2;
562+
563+
desc[0].data[2] = HCLGE_PPU_MPF_ABNORMAL_INT2_EN2_MASK;
564+
} else if (cmd == HCLGE_PPU_PF_OTHER_INT_CMD) {
565+
hclge_cmd_setup_basic_desc(&desc[0], cmd, false);
566+
if (en)
567+
desc[0].data[0] = HCLGE_PPU_PF_ABNORMAL_INT_EN;
568+
569+
desc[0].data[2] = HCLGE_PPU_PF_ABNORMAL_INT_EN_MASK;
570+
} else {
571+
dev_err(dev, "Invalid cmd to configure PPU error interrupts\n");
572+
return -EINVAL;
573+
}
574+
575+
ret = hclge_cmd_send(&hdev->hw, &desc[0], num);
576+
577+
return ret;
578+
}
579+
580+
static int hclge_config_ppu_hw_err_int(struct hclge_dev *hdev, bool en)
581+
{
582+
struct device *dev = &hdev->pdev->dev;
583+
int ret;
584+
585+
ret = hclge_config_ppu_error_interrupts(hdev, HCLGE_PPU_MPF_ECC_INT_CMD,
586+
en);
587+
if (ret) {
588+
dev_err(dev, "fail(%d) to configure PPU MPF ECC error intr\n",
589+
ret);
590+
return ret;
591+
}
592+
593+
ret = hclge_config_ppu_error_interrupts(hdev,
594+
HCLGE_PPU_MPF_OTHER_INT_CMD,
595+
en);
596+
if (ret) {
597+
dev_err(dev, "fail(%d) to configure PPU MPF other intr\n", ret);
598+
return ret;
599+
}
600+
601+
ret = hclge_config_ppu_error_interrupts(hdev,
602+
HCLGE_PPU_PF_OTHER_INT_CMD, en);
603+
if (ret)
604+
dev_err(dev, "fail(%d) to configure PPU PF error interrupts\n",
605+
ret);
606+
return ret;
607+
}
608+
492609
#define HCLGE_SET_DEFAULT_RESET_REQUEST(reset_type) \
493610
do { \
494611
if (ae_dev->ops->set_default_reset_request) \
@@ -578,6 +695,29 @@ static int hclge_handle_mpf_ras_error(struct hclge_dev *hdev,
578695
hclge_log_error(dev, "PPP_MPF_ABNORMAL_INT_ST3",
579696
&hclge_ppp_mpf_abnormal_int_st3[0], status);
580697

698+
/* log PPU(RCB) errors */
699+
desc_data = (__le32 *)&desc[5];
700+
status = le32_to_cpu(*(desc_data + 1));
701+
if (status) {
702+
dev_warn(dev, "PPU_MPF_ABNORMAL_INT_ST1 %s found\n",
703+
"rpu_rx_pkt_ecc_mbit_err");
704+
HCLGE_SET_DEFAULT_RESET_REQUEST(HNAE3_CORE_RESET);
705+
}
706+
707+
status = le32_to_cpu(*(desc_data + 2));
708+
if (status) {
709+
hclge_log_error(dev, "PPU_MPF_ABNORMAL_INT_ST2",
710+
&hclge_ppu_mpf_abnormal_int_st2[0], status);
711+
HCLGE_SET_DEFAULT_RESET_REQUEST(HNAE3_CORE_RESET);
712+
}
713+
714+
status = le32_to_cpu(*(desc_data + 3)) & HCLGE_PPU_MPF_INT_ST3_MASK;
715+
if (status) {
716+
hclge_log_error(dev, "PPU_MPF_ABNORMAL_INT_ST3",
717+
&hclge_ppu_mpf_abnormal_int_st3[0], status);
718+
HCLGE_SET_DEFAULT_RESET_REQUEST(HNAE3_CORE_RESET);
719+
}
720+
581721
/* log TM(Traffic Manager) errors */
582722
desc_data = (__le32 *)&desc[6];
583723
status = le32_to_cpu(*desc_data);
@@ -717,6 +857,10 @@ static const struct hclge_hw_blk hw_blk[] = {
717857
.msk = BIT(1), .name = "PPP",
718858
.config_err_int = hclge_config_ppp_hw_err_int,
719859
},
860+
{
861+
.msk = BIT(3), .name = "PPU",
862+
.config_err_int = hclge_config_ppu_hw_err_int,
863+
},
720864
{
721865
.msk = BIT(4), .name = "TM",
722866
.config_err_int = hclge_config_tm_hw_err_int,
@@ -826,6 +970,17 @@ int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
826970
set_bit(HNAE3_GLOBAL_RESET, reset_requests);
827971
}
828972

973+
/* log PPU(RCB) errors */
974+
desc_data = (__le32 *)&desc[5];
975+
status = le32_to_cpu(*(desc_data + 2)) &
976+
HCLGE_PPU_MPF_INT_ST2_MSIX_MASK;
977+
if (status) {
978+
dev_warn(dev,
979+
"PPU_MPF_ABNORMAL_INT_ST2[28:29], err_status(0x%x)\n",
980+
status);
981+
set_bit(HNAE3_CORE_RESET, reset_requests);
982+
}
983+
829984
/* clear all main PF MSIx errors */
830985
hclge_cmd_reuse_desc(&desc[0], false);
831986
desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
@@ -861,6 +1016,13 @@ int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
8611016
hclge_log_error(dev, "PPP_PF_ABNORMAL_INT_ST0",
8621017
&hclge_ppp_pf_abnormal_int[0], status);
8631018

1019+
/* PPU(RCB) PF errors */
1020+
desc_data = (__le32 *)&desc[3];
1021+
status = le32_to_cpu(*desc_data) & HCLGE_PPU_PF_INT_MSIX_MASK;
1022+
if (status)
1023+
hclge_log_error(dev, "PPU_PF_ABNORMAL_INT_ST",
1024+
&hclge_ppu_pf_abnormal_int[0], status);
1025+
8641026
/* clear all PF MSIx errors */
8651027
hclge_cmd_reuse_desc(&desc[0], false);
8661028
desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);

‎drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,10 +46,25 @@
4646
#define HCLGE_NCSI_ERR_INT_TYPE 0x9
4747
#define HCLGE_MAC_COMMON_ERR_INT_EN GENMASK(7, 0)
4848
#define HCLGE_MAC_COMMON_ERR_INT_EN_MASK GENMASK(7, 0)
49+
#define HCLGE_PPU_MPF_ABNORMAL_INT0_EN GENMASK(31, 0)
50+
#define HCLGE_PPU_MPF_ABNORMAL_INT0_EN_MASK GENMASK(31, 0)
51+
#define HCLGE_PPU_MPF_ABNORMAL_INT1_EN GENMASK(31, 0)
52+
#define HCLGE_PPU_MPF_ABNORMAL_INT1_EN_MASK GENMASK(31, 0)
53+
#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN 0x3FFF3FFF
54+
#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN_MASK 0x3FFF3FFF
55+
#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2 0xB
56+
#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2_MASK 0xB
57+
#define HCLGE_PPU_MPF_ABNORMAL_INT3_EN GENMASK(7, 0)
58+
#define HCLGE_PPU_MPF_ABNORMAL_INT3_EN_MASK GENMASK(23, 16)
59+
#define HCLGE_PPU_PF_ABNORMAL_INT_EN GENMASK(5, 0)
60+
#define HCLGE_PPU_PF_ABNORMAL_INT_EN_MASK GENMASK(5, 0)
4961

5062
#define HCLGE_IGU_INT_MASK GENMASK(3, 0)
5163
#define HCLGE_IGU_EGU_TNL_INT_MASK GENMASK(5, 0)
5264
#define HCLGE_PPP_MPF_INT_ST3_MASK GENMASK(5, 0)
65+
#define HCLGE_PPU_MPF_INT_ST3_MASK GENMASK(7, 0)
66+
#define HCLGE_PPU_MPF_INT_ST2_MSIX_MASK GENMASK(29, 28)
67+
#define HCLGE_PPU_PF_INT_MSIX_MASK 0x27
5368
#define HCLGE_QCN_FIFO_INT_MASK GENMASK(17, 0)
5469
#define HCLGE_QCN_ECC_INT_MASK GENMASK(21, 0)
5570
#define HCLGE_NCSI_ECC_INT_MASK GENMASK(1, 0)

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