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maurossialexdeucher
maurossi
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alexdeucher
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drm/amd/display: dce_opp: add DCE6 specific macros,functions
[Why] DCE6 has no FMT_TRUNCATE_MODE bit in FMT_BIT_DEPTH_CONTROL register DCE6 has no FMT_CLAMP_COMPONENT_{R,G,B} registers DCE6 has no FMT_SUBSAMPLING_{MODE,ORDER} bits in FMT_CONTROL register [How] Add DCE6 specific macros definitions for OPP registers and masks DCE6 OPP macros will avoid buiding errors when using DCE6 headers Add dce60_set_truncation() w/o FMT_TRUNCATE_MODE bit programming Add dce60_opp_set_clamping() w/o Format Clamp Component programming Add dce60_opp_program_fmt() w/o Format Subsampling bits programming Add dce60_opp_program_bit_depth_reduction() with dce60_set_truncation Use dce60_opp_program_fmt() in dce60_opp_funcs Use dce60_opp_program_bit_depth_reduction() in dce60_opp_funcs Add DCE6 specific dce60_opp_construct Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Mauro Rossi <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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‎drivers/gpu/drm/amd/display/dc/dce/dce_opp.c‎

Lines changed: 205 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -141,6 +141,47 @@ static void set_truncation(
141141
params->flags.TRUNCATE_MODE);
142142
}
143143

144+
#if defined(CONFIG_DRM_AMD_DC_SI)
145+
/**
146+
* dce60_set_truncation
147+
* 1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp
148+
* 2) enable truncation
149+
* 3) HW remove 12bit FMT support for DCE11 power saving reason.
150+
*/
151+
static void dce60_set_truncation(
152+
struct dce110_opp *opp110,
153+
const struct bit_depth_reduction_params *params)
154+
{
155+
/* DCE6 has no FMT_TRUNCATE_MODE bit in FMT_BIT_DEPTH_CONTROL reg */
156+
157+
/*Disable truncation*/
158+
REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,
159+
FMT_TRUNCATE_EN, 0,
160+
FMT_TRUNCATE_DEPTH, 0);
161+
162+
if (params->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
163+
/* 8bpc trunc on YCbCr422*/
164+
if (params->flags.TRUNCATE_DEPTH == 1)
165+
REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,
166+
FMT_TRUNCATE_EN, 1,
167+
FMT_TRUNCATE_DEPTH, 1);
168+
else if (params->flags.TRUNCATE_DEPTH == 2)
169+
/* 10bpc trunc on YCbCr422*/
170+
REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,
171+
FMT_TRUNCATE_EN, 1,
172+
FMT_TRUNCATE_DEPTH, 2);
173+
return;
174+
}
175+
/* on other format-to do */
176+
if (params->flags.TRUNCATE_ENABLED == 0)
177+
return;
178+
/*Set truncation depth and Enable truncation*/
179+
REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,
180+
FMT_TRUNCATE_EN, 1,
181+
FMT_TRUNCATE_DEPTH,
182+
params->flags.TRUNCATE_DEPTH);
183+
}
184+
#endif
144185

145186
/**
146187
* set_spatial_dither
@@ -373,6 +414,57 @@ void dce110_opp_set_clamping(
373414
}
374415
}
375416

417+
#if defined(CONFIG_DRM_AMD_DC_SI)
418+
/**
419+
* Set Clamping for DCE6 parts
420+
* 1) Set clamping format based on bpc - 0 for 6bpc (No clamping)
421+
* 1 for 8 bpc
422+
* 2 for 10 bpc
423+
* 3 for 12 bpc
424+
* 7 for programable
425+
* 2) Enable clamp if Limited range requested
426+
*/
427+
void dce60_opp_set_clamping(
428+
struct dce110_opp *opp110,
429+
const struct clamping_and_pixel_encoding_params *params)
430+
{
431+
REG_SET_2(FMT_CLAMP_CNTL, 0,
432+
FMT_CLAMP_DATA_EN, 0,
433+
FMT_CLAMP_COLOR_FORMAT, 0);
434+
435+
switch (params->clamping_level) {
436+
case CLAMPING_FULL_RANGE:
437+
break;
438+
case CLAMPING_LIMITED_RANGE_8BPC:
439+
REG_SET_2(FMT_CLAMP_CNTL, 0,
440+
FMT_CLAMP_DATA_EN, 1,
441+
FMT_CLAMP_COLOR_FORMAT, 1);
442+
break;
443+
case CLAMPING_LIMITED_RANGE_10BPC:
444+
REG_SET_2(FMT_CLAMP_CNTL, 0,
445+
FMT_CLAMP_DATA_EN, 1,
446+
FMT_CLAMP_COLOR_FORMAT, 2);
447+
break;
448+
case CLAMPING_LIMITED_RANGE_12BPC:
449+
REG_SET_2(FMT_CLAMP_CNTL, 0,
450+
FMT_CLAMP_DATA_EN, 1,
451+
FMT_CLAMP_COLOR_FORMAT, 3);
452+
break;
453+
case CLAMPING_LIMITED_RANGE_PROGRAMMABLE:
454+
/*Set clamp control*/
455+
REG_SET_2(FMT_CLAMP_CNTL, 0,
456+
FMT_CLAMP_DATA_EN, 1,
457+
FMT_CLAMP_COLOR_FORMAT, 7);
458+
459+
/* DCE6 does have FMT_CLAMP_COMPONENT_{R,G,B} registers */
460+
461+
break;
462+
default:
463+
break;
464+
}
465+
}
466+
#endif
467+
376468
/**
377469
* set_pixel_encoding
378470
*
@@ -408,6 +500,39 @@ static void set_pixel_encoding(
408500

409501
}
410502

503+
#if defined(CONFIG_DRM_AMD_DC_SI)
504+
/**
505+
* dce60_set_pixel_encoding
506+
* DCE6 has no FMT_SUBSAMPLING_{MODE,ORDER} bits in FMT_CONTROL reg
507+
* Set Pixel Encoding
508+
* 0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly
509+
* 1: YCbCr 4:2:2
510+
*/
511+
static void dce60_set_pixel_encoding(
512+
struct dce110_opp *opp110,
513+
const struct clamping_and_pixel_encoding_params *params)
514+
{
515+
if (opp110->opp_mask->FMT_CBCR_BIT_REDUCTION_BYPASS)
516+
REG_UPDATE_2(FMT_CONTROL,
517+
FMT_PIXEL_ENCODING, 0,
518+
FMT_CBCR_BIT_REDUCTION_BYPASS, 0);
519+
else
520+
REG_UPDATE(FMT_CONTROL,
521+
FMT_PIXEL_ENCODING, 0);
522+
523+
if (params->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
524+
REG_UPDATE(FMT_CONTROL,
525+
FMT_PIXEL_ENCODING, 1);
526+
}
527+
if (params->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
528+
REG_UPDATE_2(FMT_CONTROL,
529+
FMT_PIXEL_ENCODING, 2,
530+
FMT_CBCR_BIT_REDUCTION_BYPASS, 1);
531+
}
532+
533+
}
534+
#endif
535+
411536
void dce110_opp_program_bit_depth_reduction(
412537
struct output_pixel_processor *opp,
413538
const struct bit_depth_reduction_params *params)
@@ -419,6 +544,19 @@ void dce110_opp_program_bit_depth_reduction(
419544
set_temporal_dither(opp110, params);
420545
}
421546

547+
#if defined(CONFIG_DRM_AMD_DC_SI)
548+
void dce60_opp_program_bit_depth_reduction(
549+
struct output_pixel_processor *opp,
550+
const struct bit_depth_reduction_params *params)
551+
{
552+
struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
553+
554+
dce60_set_truncation(opp110, params);
555+
set_spatial_dither(opp110, params);
556+
set_temporal_dither(opp110, params);
557+
}
558+
#endif
559+
422560
void dce110_opp_program_clamping_and_pixel_encoding(
423561
struct output_pixel_processor *opp,
424562
const struct clamping_and_pixel_encoding_params *params)
@@ -429,6 +567,19 @@ void dce110_opp_program_clamping_and_pixel_encoding(
429567
set_pixel_encoding(opp110, params);
430568
}
431569

570+
#if defined(CONFIG_DRM_AMD_DC_SI)
571+
void dce60_opp_program_clamping_and_pixel_encoding(
572+
struct output_pixel_processor *opp,
573+
const struct clamping_and_pixel_encoding_params *params)
574+
{
575+
struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
576+
577+
dce60_opp_set_clamping(opp110, params);
578+
dce60_set_pixel_encoding(opp110, params);
579+
}
580+
#endif
581+
582+
432583
static void program_formatter_420_memory(struct output_pixel_processor *opp)
433584
{
434585
struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
@@ -526,7 +677,32 @@ void dce110_opp_program_fmt(
526677
return;
527678
}
528679

680+
#if defined(CONFIG_DRM_AMD_DC_SI)
681+
void dce60_opp_program_fmt(
682+
struct output_pixel_processor *opp,
683+
struct bit_depth_reduction_params *fmt_bit_depth,
684+
struct clamping_and_pixel_encoding_params *clamping)
685+
{
686+
/* dithering is affected by <CrtcSourceSelect>, hence should be
687+
* programmed afterwards */
688+
689+
if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420)
690+
program_formatter_420_memory(opp);
691+
692+
dce60_opp_program_bit_depth_reduction(
693+
opp,
694+
fmt_bit_depth);
695+
696+
dce60_opp_program_clamping_and_pixel_encoding(
697+
opp,
698+
clamping);
699+
700+
if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420)
701+
program_formatter_reset_dig_resync_fifo(opp);
529702

703+
return;
704+
}
705+
#endif
530706

531707

532708

@@ -541,6 +717,15 @@ static const struct opp_funcs funcs = {
541717
.opp_program_bit_depth_reduction = dce110_opp_program_bit_depth_reduction
542718
};
543719

720+
#if defined(CONFIG_DRM_AMD_DC_SI)
721+
static const struct opp_funcs dce60_opp_funcs = {
722+
.opp_set_dyn_expansion = dce110_opp_set_dyn_expansion,
723+
.opp_destroy = dce110_opp_destroy,
724+
.opp_program_fmt = dce60_opp_program_fmt,
725+
.opp_program_bit_depth_reduction = dce60_opp_program_bit_depth_reduction
726+
};
727+
#endif
728+
544729
void dce110_opp_construct(struct dce110_opp *opp110,
545730
struct dc_context *ctx,
546731
uint32_t inst,
@@ -559,6 +744,26 @@ void dce110_opp_construct(struct dce110_opp *opp110,
559744
opp110->opp_mask = opp_mask;
560745
}
561746

747+
#if defined(CONFIG_DRM_AMD_DC_SI)
748+
void dce60_opp_construct(struct dce110_opp *opp110,
749+
struct dc_context *ctx,
750+
uint32_t inst,
751+
const struct dce_opp_registers *regs,
752+
const struct dce_opp_shift *opp_shift,
753+
const struct dce_opp_mask *opp_mask)
754+
{
755+
opp110->base.funcs = &dce60_opp_funcs;
756+
757+
opp110->base.ctx = ctx;
758+
759+
opp110->base.inst = inst;
760+
761+
opp110->regs = regs;
762+
opp110->opp_shift = opp_shift;
763+
opp110->opp_mask = opp_mask;
764+
}
765+
#endif
766+
562767
void dce110_opp_destroy(struct output_pixel_processor **opp)
563768
{
564769
if (*opp)

‎drivers/gpu/drm/amd/display/dc/dce/dce_opp.h‎

Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -81,6 +81,17 @@ enum dce110_opp_reg_type {
8181
OPP_COMMON_REG_LIST_BASE(id), \
8282
SRI(CONTROL, FMT_MEMORY, id)
8383

84+
#if defined(CONFIG_DRM_AMD_DC_SI)
85+
#define OPP_DCE_60_REG_LIST(id) \
86+
SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
87+
SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
88+
SRI(FMT_CONTROL, FMT, id), \
89+
SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \
90+
SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \
91+
SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \
92+
SRI(FMT_CLAMP_CNTL, FMT, id)
93+
#endif
94+
8495
#define OPP_SF(reg_name, field_name, post_fix)\
8596
.field_name = reg_name ## __ ## field_name ## post_fix
8697

@@ -192,6 +203,35 @@ enum dce110_opp_reg_type {
192203
OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh),\
193204
OPP_SF(FMT0_FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh)
194205

206+
#if defined(CONFIG_DRM_AMD_DC_SI)
207+
#define OPP_COMMON_MASK_SH_LIST_DCE_60(mask_sh)\
208+
OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\
209+
OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\
210+
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\
211+
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\
212+
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\
213+
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\
214+
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\
215+
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\
216+
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\
217+
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\
218+
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\
219+
OPP_SF(FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\
220+
OPP_SF(FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\
221+
OPP_SF(FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\
222+
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\
223+
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\
224+
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\
225+
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\
226+
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\
227+
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\
228+
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\
229+
OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\
230+
OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\
231+
OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\
232+
OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh)
233+
#endif
234+
195235
#define OPP_REG_FIELD_LIST(type) \
196236
type FMT_DYNAMIC_EXP_EN; \
197237
type FMT_DYNAMIC_EXP_MODE; \
@@ -279,6 +319,15 @@ void dce110_opp_construct(struct dce110_opp *opp110,
279319
const struct dce_opp_shift *opp_shift,
280320
const struct dce_opp_mask *opp_mask);
281321

322+
#if defined(CONFIG_DRM_AMD_DC_SI)
323+
void dce60_opp_construct(struct dce110_opp *opp110,
324+
struct dc_context *ctx,
325+
uint32_t inst,
326+
const struct dce_opp_registers *regs,
327+
const struct dce_opp_shift *opp_shift,
328+
const struct dce_opp_mask *opp_mask);
329+
#endif
330+
282331
void dce110_opp_destroy(struct output_pixel_processor **opp);
283332

284333

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