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maurossialexdeucher
maurossi
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alexdeucher
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drm/amd/display: dce_mem_input: add DCE6 specific macros,functions (v2)
[Why] DCE6 has DPG_PIPE_ARBITRATION_CONTROL3 register for Line Buffer watermark selection DCE6 has STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK mask for Stutter watermark selection DCE6 has NB_PSTATE_CHANGE_WATERMARK_MASK mask for North Bridge watermark selection DCE6 has no GRPH_MICRO_TILE_MODE mask DCE6 has no HW_ROTATION register [How] Add DCE6 specific macros definitions for MI registers and masks Add DCE6 specific registers to dce_mem_input_registers struct Add DCE6 specific masks to dce_mem_input_masks struct DCE6 MI macros/structs changes will avoid buiding errors when using DCE6 headers Add dce60_program_urgency_watermark() function Add dce60_program_nbp_watermark() function Add dce60_program_stutter_watermark() function Add dce60_mi_program_display_marks() function w/ new DCE6 watermark programming Add DCE6 specific tiling programming and modify DCE8 case Add dce60_program_size() fuction w/o Rotation processing Add dce60_mi_program_surface_config() fuction Use dce60_mi_program_display_marks() in dce60_mi_funcs Use dce60_mi_program_surface_config() in dce60_mi_funcs Add DCE6 specific dce60_mem_input_construct v2: remove unused variable (Alex) Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Mauro Rossi <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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‎drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c‎

Lines changed: 175 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -174,6 +174,22 @@ static void program_urgency_watermark(
174174
URGENCY_HIGH_WATERMARK, urgency_high_wm);
175175
}
176176

177+
#if defined(CONFIG_DRM_AMD_DC_SI)
178+
static void dce60_program_urgency_watermark(
179+
struct dce_mem_input *dce_mi,
180+
uint32_t wm_select,
181+
uint32_t urgency_low_wm,
182+
uint32_t urgency_high_wm)
183+
{
184+
REG_UPDATE(DPG_PIPE_ARBITRATION_CONTROL3,
185+
URGENCY_WATERMARK_MASK, wm_select);
186+
187+
REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0,
188+
URGENCY_LOW_WATERMARK, urgency_low_wm,
189+
URGENCY_HIGH_WATERMARK, urgency_high_wm);
190+
}
191+
#endif
192+
177193
static void dce120_program_urgency_watermark(
178194
struct dce_mem_input *dce_mi,
179195
uint32_t wm_select,
@@ -193,6 +209,25 @@ static void dce120_program_urgency_watermark(
193209

194210
}
195211

212+
#if defined(CONFIG_DRM_AMD_DC_SI)
213+
static void dce60_program_nbp_watermark(
214+
struct dce_mem_input *dce_mi,
215+
uint32_t wm_select,
216+
uint32_t nbp_wm)
217+
{
218+
REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
219+
NB_PSTATE_CHANGE_WATERMARK_MASK, wm_select);
220+
221+
REG_UPDATE_3(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
222+
NB_PSTATE_CHANGE_ENABLE, 1,
223+
NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, 1,
224+
NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, 1);
225+
226+
REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
227+
NB_PSTATE_CHANGE_WATERMARK, nbp_wm);
228+
}
229+
#endif
230+
196231
static void program_nbp_watermark(
197232
struct dce_mem_input *dce_mi,
198233
uint32_t wm_select,
@@ -225,6 +260,20 @@ static void program_nbp_watermark(
225260
}
226261
}
227262

263+
#if defined(CONFIG_DRM_AMD_DC_SI)
264+
static void dce60_program_stutter_watermark(
265+
struct dce_mem_input *dce_mi,
266+
uint32_t wm_select,
267+
uint32_t stutter_mark)
268+
{
269+
REG_UPDATE(DPG_PIPE_STUTTER_CONTROL,
270+
STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, wm_select);
271+
272+
REG_UPDATE(DPG_PIPE_STUTTER_CONTROL,
273+
STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark);
274+
}
275+
#endif
276+
228277
static void dce120_program_stutter_watermark(
229278
struct dce_mem_input *dce_mi,
230279
uint32_t wm_select,
@@ -286,6 +335,34 @@ static void dce_mi_program_display_marks(
286335
program_stutter_watermark(dce_mi, 1, stutter_exit.d_mark); /* set d */
287336
}
288337

338+
#if defined(CONFIG_DRM_AMD_DC_SI)
339+
static void dce60_mi_program_display_marks(
340+
struct mem_input *mi,
341+
struct dce_watermarks nbp,
342+
struct dce_watermarks stutter_exit,
343+
struct dce_watermarks stutter_enter,
344+
struct dce_watermarks urgent,
345+
uint32_t total_dest_line_time_ns)
346+
{
347+
struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
348+
uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;
349+
350+
dce60_program_urgency_watermark(dce_mi, 2, /* set a */
351+
urgent.a_mark, total_dest_line_time_ns);
352+
dce60_program_urgency_watermark(dce_mi, 1, /* set d */
353+
urgent.d_mark, total_dest_line_time_ns);
354+
355+
REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
356+
STUTTER_ENABLE, stutter_en,
357+
STUTTER_IGNORE_FBC, 1);
358+
dce60_program_nbp_watermark(dce_mi, 2, nbp.a_mark); /* set a */
359+
dce60_program_nbp_watermark(dce_mi, 1, nbp.d_mark); /* set d */
360+
361+
dce60_program_stutter_watermark(dce_mi, 2, stutter_exit.a_mark); /* set a */
362+
dce60_program_stutter_watermark(dce_mi, 1, stutter_exit.d_mark); /* set d */
363+
}
364+
#endif
365+
289366
static void dce112_mi_program_display_marks(struct mem_input *mi,
290367
struct dce_watermarks nbp,
291368
struct dce_watermarks stutter_exit,
@@ -369,7 +446,7 @@ static void program_tiling(
369446
*/
370447
}
371448

372-
if (dce_mi->masks->GRPH_ARRAY_MODE) { /* GFX8 */
449+
if (dce_mi->masks->GRPH_MICRO_TILE_MODE) { /* GFX8 */
373450
REG_UPDATE_9(GRPH_CONTROL,
374451
GRPH_NUM_BANKS, info->gfx8.num_banks,
375452
GRPH_BANK_WIDTH, info->gfx8.bank_width,
@@ -385,6 +462,23 @@ static void program_tiling(
385462
GRPH_Z, 0);
386463
*/
387464
}
465+
466+
if (dce_mi->masks->GRPH_ARRAY_MODE) { /* GFX6 but reuses gfx8 struct */
467+
REG_UPDATE_8(GRPH_CONTROL,
468+
GRPH_NUM_BANKS, info->gfx8.num_banks,
469+
GRPH_BANK_WIDTH, info->gfx8.bank_width,
470+
GRPH_BANK_HEIGHT, info->gfx8.bank_height,
471+
GRPH_MACRO_TILE_ASPECT, info->gfx8.tile_aspect,
472+
GRPH_TILE_SPLIT, info->gfx8.tile_split,
473+
/* DCE6 has no GRPH_MICRO_TILE_MODE mask */
474+
GRPH_PIPE_CONFIG, info->gfx8.pipe_config,
475+
GRPH_ARRAY_MODE, info->gfx8.array_mode,
476+
GRPH_COLOR_EXPANSION_MODE, 1);
477+
/* 01 - DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP: zero expansion for YCbCr */
478+
/*
479+
GRPH_Z, 0);
480+
*/
481+
}
388482
}
389483

390484

@@ -429,6 +523,36 @@ static void program_size_and_rotation(
429523
GRPH_ROTATION_ANGLE, rotation_angles[rotation]);
430524
}
431525

526+
#if defined(CONFIG_DRM_AMD_DC_SI)
527+
static void dce60_program_size(
528+
struct dce_mem_input *dce_mi,
529+
enum dc_rotation_angle rotation, /* not used in DCE6 */
530+
const struct plane_size *plane_size)
531+
{
532+
struct rect hw_rect = plane_size->surface_size;
533+
/* DCE6 has no HW rotation, skip rotation_angles declaration */
534+
535+
/* DCE6 has no HW rotation, skip ROTATION_ANGLE_* processing */
536+
537+
REG_SET(GRPH_X_START, 0,
538+
GRPH_X_START, hw_rect.x);
539+
540+
REG_SET(GRPH_Y_START, 0,
541+
GRPH_Y_START, hw_rect.y);
542+
543+
REG_SET(GRPH_X_END, 0,
544+
GRPH_X_END, hw_rect.width);
545+
546+
REG_SET(GRPH_Y_END, 0,
547+
GRPH_Y_END, hw_rect.height);
548+
549+
REG_SET(GRPH_PITCH, 0,
550+
GRPH_PITCH, plane_size->surface_pitch);
551+
552+
/* DCE6 has no HW_ROTATION register, skip setting rotation_angles */
553+
}
554+
#endif
555+
432556
static void program_grph_pixel_format(
433557
struct dce_mem_input *dce_mi,
434558
enum surface_pixel_format format)
@@ -521,6 +645,28 @@ static void dce_mi_program_surface_config(
521645
program_grph_pixel_format(dce_mi, format);
522646
}
523647

648+
#if defined(CONFIG_DRM_AMD_DC_SI)
649+
static void dce60_mi_program_surface_config(
650+
struct mem_input *mi,
651+
enum surface_pixel_format format,
652+
union dc_tiling_info *tiling_info,
653+
struct plane_size *plane_size,
654+
enum dc_rotation_angle rotation, /* not used in DCE6 */
655+
struct dc_plane_dcc_param *dcc,
656+
bool horizontal_mirror)
657+
{
658+
struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
659+
REG_UPDATE(GRPH_ENABLE, GRPH_ENABLE, 1);
660+
661+
program_tiling(dce_mi, tiling_info);
662+
dce60_program_size(dce_mi, rotation, plane_size);
663+
664+
if (format >= SURFACE_PIXEL_FORMAT_GRPH_BEGIN &&
665+
format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
666+
program_grph_pixel_format(dce_mi, format);
667+
}
668+
#endif
669+
524670
static uint32_t get_dmif_switch_time_us(
525671
uint32_t h_total,
526672
uint32_t v_total,
@@ -741,6 +887,20 @@ static const struct mem_input_funcs dce_mi_funcs = {
741887
.mem_input_is_flip_pending = dce_mi_is_flip_pending
742888
};
743889

890+
#if defined(CONFIG_DRM_AMD_DC_SI)
891+
static const struct mem_input_funcs dce60_mi_funcs = {
892+
.mem_input_program_display_marks = dce60_mi_program_display_marks,
893+
.allocate_mem_input = dce_mi_allocate_dmif,
894+
.free_mem_input = dce_mi_free_dmif,
895+
.mem_input_program_surface_flip_and_addr =
896+
dce_mi_program_surface_flip_and_addr,
897+
.mem_input_program_pte_vm = dce_mi_program_pte_vm,
898+
.mem_input_program_surface_config =
899+
dce60_mi_program_surface_config,
900+
.mem_input_is_flip_pending = dce_mi_is_flip_pending
901+
};
902+
#endif
903+
744904
static const struct mem_input_funcs dce112_mi_funcs = {
745905
.mem_input_program_display_marks = dce112_mi_program_display_marks,
746906
.allocate_mem_input = dce_mi_allocate_dmif,
@@ -783,6 +943,20 @@ void dce_mem_input_construct(
783943
dce_mi->masks = mi_mask;
784944
}
785945

946+
#if defined(CONFIG_DRM_AMD_DC_SI)
947+
void dce60_mem_input_construct(
948+
struct dce_mem_input *dce_mi,
949+
struct dc_context *ctx,
950+
int inst,
951+
const struct dce_mem_input_registers *regs,
952+
const struct dce_mem_input_shift *mi_shift,
953+
const struct dce_mem_input_mask *mi_mask)
954+
{
955+
dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask);
956+
dce_mi->base.funcs = &dce60_mi_funcs;
957+
}
958+
#endif
959+
786960
void dce112_mem_input_construct(
787961
struct dce_mem_input *dce_mi,
788962
struct dc_context *ctx,

‎drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h‎

Lines changed: 103 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,31 @@
5858
SRI(DVMM_PTE_CONTROL, DCP, id),\
5959
SRI(DVMM_PTE_ARB_CONTROL, DCP, id)
6060

61+
#if defined(CONFIG_DRM_AMD_DC_SI)
62+
#define MI_DCE6_REG_LIST(id)\
63+
SRI(GRPH_ENABLE, DCP, id),\
64+
SRI(GRPH_CONTROL, DCP, id),\
65+
SRI(GRPH_X_START, DCP, id),\
66+
SRI(GRPH_Y_START, DCP, id),\
67+
SRI(GRPH_X_END, DCP, id),\
68+
SRI(GRPH_Y_END, DCP, id),\
69+
SRI(GRPH_PITCH, DCP, id),\
70+
SRI(GRPH_SWAP_CNTL, DCP, id),\
71+
SRI(PRESCALE_GRPH_CONTROL, DCP, id),\
72+
SRI(GRPH_UPDATE, DCP, id),\
73+
SRI(GRPH_FLIP_CONTROL, DCP, id),\
74+
SRI(GRPH_PRIMARY_SURFACE_ADDRESS, DCP, id),\
75+
SRI(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, DCP, id),\
76+
SRI(GRPH_SECONDARY_SURFACE_ADDRESS, DCP, id),\
77+
SRI(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, DCP, id),\
78+
SRI(DPG_PIPE_ARBITRATION_CONTROL1, DMIF_PG, id),\
79+
SRI(DPG_PIPE_ARBITRATION_CONTROL3, DMIF_PG, id),\
80+
SRI(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, DMIF_PG, id),\
81+
SRI(DPG_PIPE_URGENCY_CONTROL, DMIF_PG, id),\
82+
SRI(DPG_PIPE_STUTTER_CONTROL, DMIF_PG, id),\
83+
SRI(DMIF_BUFFER_CONTROL, PIPE, id)
84+
#endif
85+
6186
#define MI_DCE8_REG_LIST(id)\
6287
MI_DCE_BASE_REG_LIST(id),\
6388
SRI(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, DMIF_PG, id)
@@ -104,6 +129,9 @@ struct dce_mem_input_registers {
104129
uint32_t GRPH_SECONDARY_SURFACE_ADDRESS_HIGH;
105130
/* DMIF_PG */
106131
uint32_t DPG_PIPE_ARBITRATION_CONTROL1;
132+
#if defined(CONFIG_DRM_AMD_DC_SI)
133+
uint32_t DPG_PIPE_ARBITRATION_CONTROL3;
134+
#endif
107135
uint32_t DPG_WATERMARK_MASK_CONTROL;
108136
uint32_t DPG_PIPE_URGENCY_CONTROL;
109137
uint32_t DPG_PIPE_URGENT_LEVEL_CONTROL;
@@ -126,6 +154,18 @@ struct dce_mem_input_registers {
126154
#define SFB(blk_name, reg_name, field_name, post_fix)\
127155
.field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
128156

157+
#if defined(CONFIG_DRM_AMD_DC_SI)
158+
#define MI_GFX6_TILE_MASK_SH_LIST(mask_sh, blk)\
159+
SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
160+
SFB(blk, GRPH_CONTROL, GRPH_BANK_WIDTH, mask_sh),\
161+
SFB(blk, GRPH_CONTROL, GRPH_BANK_HEIGHT, mask_sh),\
162+
SFB(blk, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, mask_sh),\
163+
SFB(blk, GRPH_CONTROL, GRPH_TILE_SPLIT, mask_sh),\
164+
SFB(blk, GRPH_CONTROL, GRPH_PIPE_CONFIG, mask_sh),\
165+
SFB(blk, GRPH_CONTROL, GRPH_ARRAY_MODE, mask_sh),\
166+
SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh)
167+
#endif
168+
129169
#define MI_GFX8_TILE_MASK_SH_LIST(mask_sh, blk)\
130170
SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
131171
SFB(blk, GRPH_CONTROL, GRPH_BANK_WIDTH, mask_sh),\
@@ -162,6 +202,32 @@ struct dce_mem_input_registers {
162202
SFB(blk, GRPH_UPDATE, GRPH_UPDATE_LOCK, mask_sh),\
163203
SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, mask_sh)
164204

205+
#if defined(CONFIG_DRM_AMD_DC_SI)
206+
#define MI_DCP_MASK_SH_LIST_DCE6(mask_sh, blk)\
207+
SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\
208+
SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\
209+
SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\
210+
SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
211+
SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\
212+
SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\
213+
SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\
214+
SFB(blk, GRPH_Y_END, GRPH_Y_END, mask_sh),\
215+
SFB(blk, GRPH_PITCH, GRPH_PITCH, mask_sh),\
216+
SFB(blk, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, mask_sh),\
217+
SFB(blk, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, mask_sh),\
218+
SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_SELECT, mask_sh),\
219+
SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_R_SIGN, mask_sh),\
220+
SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\
221+
SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh),\
222+
SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
223+
SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_SURFACE_ADDRESS, mask_sh),\
224+
SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
225+
SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS, GRPH_PRIMARY_SURFACE_ADDRESS, mask_sh),\
226+
SFB(blk, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, mask_sh),\
227+
SFB(blk, GRPH_UPDATE, GRPH_UPDATE_LOCK, mask_sh),\
228+
SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, mask_sh)
229+
#endif
230+
165231
#define MI_DCP_DCE11_MASK_SH_LIST(mask_sh, blk)\
166232
SFB(blk, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, mask_sh)
167233

@@ -172,6 +238,33 @@ struct dce_mem_input_registers {
172238
SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_PTE_REQ_PER_CHUNK, mask_sh),\
173239
SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_MAX_PTE_REQ_OUTSTANDING, mask_sh)
174240

241+
#if defined(CONFIG_DRM_AMD_DC_SI)
242+
#define MI_DMIF_PG_MASK_SH_LIST_DCE6(mask_sh, blk)\
243+
SFB(blk, DPG_PIPE_ARBITRATION_CONTROL1, PIXEL_DURATION, mask_sh),\
244+
SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\
245+
SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\
246+
SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE, mask_sh),\
247+
SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_IGNORE_FBC, mask_sh),\
248+
SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\
249+
SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)
250+
251+
#define MI_DMIF_PG_MASK_SH_DCE6(mask_sh, blk)\
252+
SFB(blk, DPG_PIPE_ARBITRATION_CONTROL3, URGENCY_WATERMARK_MASK, mask_sh),\
253+
SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, mask_sh),\
254+
SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\
255+
SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
256+
SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_ENABLE, mask_sh),\
257+
SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
258+
SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\
259+
SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK, mask_sh)
260+
261+
#define MI_DCE6_MASK_SH_LIST(mask_sh)\
262+
MI_DCP_MASK_SH_LIST_DCE6(mask_sh, ),\
263+
MI_DMIF_PG_MASK_SH_LIST_DCE6(mask_sh, ),\
264+
MI_DMIF_PG_MASK_SH_DCE6(mask_sh, ),\
265+
MI_GFX6_TILE_MASK_SH_LIST(mask_sh, )
266+
#endif
267+
175268
#define MI_DMIF_PG_MASK_SH_LIST(mask_sh, blk)\
176269
SFB(blk, DPG_PIPE_ARBITRATION_CONTROL1, PIXEL_DURATION, mask_sh),\
177270
SFB(blk, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, mask_sh),\
@@ -345,6 +438,16 @@ void dce_mem_input_construct(
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const struct dce_mem_input_shift *mi_shift,
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const struct dce_mem_input_mask *mi_mask);
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441+
#if defined(CONFIG_DRM_AMD_DC_SI)
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void dce60_mem_input_construct(
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struct dce_mem_input *dce_mi,
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struct dc_context *ctx,
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int inst,
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const struct dce_mem_input_registers *regs,
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const struct dce_mem_input_shift *mi_shift,
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const struct dce_mem_input_mask *mi_mask);
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#endif
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void dce112_mem_input_construct(
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struct dce_mem_input *dce_mi,
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struct dc_context *ctx,

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