88#include <linux/bitops.h>
99#include <linux/clk.h>
1010#include <linux/counter.h>
11+ #include <linux/interrupt.h>
1112#include <linux/kernel.h>
1213#include <linux/mod_devicetable.h>
1314#include <linux/module.h>
6869#define QEPCTL_UTE BIT(1)
6970#define QEPCTL_WDE BIT(0)
7071
72+ #define QEINT_UTO BIT(11)
73+ #define QEINT_IEL BIT(10)
74+ #define QEINT_SEL BIT(9)
75+ #define QEINT_PCM BIT(8)
76+ #define QEINT_PCR BIT(7)
77+ #define QEINT_PCO BIT(6)
78+ #define QEINT_PCU BIT(5)
79+ #define QEINT_WTO BIT(4)
80+ #define QEINT_QDC BIT(3)
81+ #define QEINT_PHE BIT(2)
82+ #define QEINT_PCE BIT(1)
83+
84+ #define QFLG_UTO BIT(11)
85+ #define QFLG_IEL BIT(10)
86+ #define QFLG_SEL BIT(9)
87+ #define QFLG_PCM BIT(8)
88+ #define QFLG_PCR BIT(7)
89+ #define QFLG_PCO BIT(6)
90+ #define QFLG_PCU BIT(5)
91+ #define QFLG_WTO BIT(4)
92+ #define QFLG_QDC BIT(3)
93+ #define QFLG_PHE BIT(2)
94+ #define QFLG_PCE BIT(1)
95+ #define QFLG_INT BIT(0)
96+
97+ #define QCLR_UTO BIT(11)
98+ #define QCLR_IEL BIT(10)
99+ #define QCLR_SEL BIT(9)
100+ #define QCLR_PCM BIT(8)
101+ #define QCLR_PCR BIT(7)
102+ #define QCLR_PCO BIT(6)
103+ #define QCLR_PCU BIT(5)
104+ #define QCLR_WTO BIT(4)
105+ #define QCLR_QDC BIT(3)
106+ #define QCLR_PHE BIT(2)
107+ #define QCLR_PCE BIT(1)
108+ #define QCLR_INT BIT(0)
109+
71110/* EQEP Inputs */
72111enum {
73112 TI_EQEP_SIGNAL_QEPA , /* QEPA/XCLK */
@@ -83,20 +122,14 @@ enum ti_eqep_count_func {
83122};
84123
85124struct ti_eqep_cnt {
86- struct counter_device counter ;
87125 struct regmap * regmap32 ;
88126 struct regmap * regmap16 ;
89127};
90128
91- static struct ti_eqep_cnt * ti_eqep_count_from_counter (struct counter_device * counter )
92- {
93- return counter_priv (counter );
94- }
95-
96129static int ti_eqep_count_read (struct counter_device * counter ,
97130 struct counter_count * count , u64 * val )
98131{
99- struct ti_eqep_cnt * priv = ti_eqep_count_from_counter (counter );
132+ struct ti_eqep_cnt * priv = counter_priv (counter );
100133 u32 cnt ;
101134
102135 regmap_read (priv -> regmap32 , QPOSCNT , & cnt );
@@ -108,7 +141,7 @@ static int ti_eqep_count_read(struct counter_device *counter,
108141static int ti_eqep_count_write (struct counter_device * counter ,
109142 struct counter_count * count , u64 val )
110143{
111- struct ti_eqep_cnt * priv = ti_eqep_count_from_counter (counter );
144+ struct ti_eqep_cnt * priv = counter_priv (counter );
112145 u32 max ;
113146
114147 regmap_read (priv -> regmap32 , QPOSMAX , & max );
@@ -122,7 +155,7 @@ static int ti_eqep_function_read(struct counter_device *counter,
122155 struct counter_count * count ,
123156 enum counter_function * function )
124157{
125- struct ti_eqep_cnt * priv = ti_eqep_count_from_counter (counter );
158+ struct ti_eqep_cnt * priv = counter_priv (counter );
126159 u32 qdecctl ;
127160
128161 regmap_read (priv -> regmap16 , QDECCTL , & qdecctl );
@@ -149,7 +182,7 @@ static int ti_eqep_function_write(struct counter_device *counter,
149182 struct counter_count * count ,
150183 enum counter_function function )
151184{
152- struct ti_eqep_cnt * priv = ti_eqep_count_from_counter (counter );
185+ struct ti_eqep_cnt * priv = counter_priv (counter );
153186 enum ti_eqep_count_func qsrc ;
154187
155188 switch (function ) {
@@ -179,7 +212,7 @@ static int ti_eqep_action_read(struct counter_device *counter,
179212 struct counter_synapse * synapse ,
180213 enum counter_synapse_action * action )
181214{
182- struct ti_eqep_cnt * priv = ti_eqep_count_from_counter (counter );
215+ struct ti_eqep_cnt * priv = counter_priv (counter );
183216 enum counter_function function ;
184217 u32 qdecctl ;
185218 int err ;
@@ -239,19 +272,56 @@ static int ti_eqep_action_read(struct counter_device *counter,
239272 }
240273}
241274
275+ static int ti_eqep_events_configure (struct counter_device * counter )
276+ {
277+ struct ti_eqep_cnt * priv = counter_priv (counter );
278+ struct counter_event_node * event_node ;
279+ u32 qeint = 0 ;
280+
281+ list_for_each_entry (event_node , & counter -> events_list , l ) {
282+ switch (event_node -> event ) {
283+ case COUNTER_EVENT_OVERFLOW :
284+ qeint |= QEINT_PCO ;
285+ break ;
286+ case COUNTER_EVENT_UNDERFLOW :
287+ qeint |= QEINT_PCU ;
288+ break ;
289+ }
290+ }
291+
292+ return regmap_write (priv -> regmap16 , QEINT , qeint );
293+ }
294+
295+ static int ti_eqep_watch_validate (struct counter_device * counter ,
296+ const struct counter_watch * watch )
297+ {
298+ switch (watch -> event ) {
299+ case COUNTER_EVENT_OVERFLOW :
300+ case COUNTER_EVENT_UNDERFLOW :
301+ if (watch -> channel != 0 )
302+ return - EINVAL ;
303+
304+ return 0 ;
305+ default :
306+ return - EINVAL ;
307+ }
308+ }
309+
242310static const struct counter_ops ti_eqep_counter_ops = {
243311 .count_read = ti_eqep_count_read ,
244312 .count_write = ti_eqep_count_write ,
245313 .function_read = ti_eqep_function_read ,
246314 .function_write = ti_eqep_function_write ,
247315 .action_read = ti_eqep_action_read ,
316+ .events_configure = ti_eqep_events_configure ,
317+ .watch_validate = ti_eqep_watch_validate ,
248318};
249319
250320static int ti_eqep_position_ceiling_read (struct counter_device * counter ,
251321 struct counter_count * count ,
252322 u64 * ceiling )
253323{
254- struct ti_eqep_cnt * priv = ti_eqep_count_from_counter (counter );
324+ struct ti_eqep_cnt * priv = counter_priv (counter );
255325 u32 qposmax ;
256326
257327 regmap_read (priv -> regmap32 , QPOSMAX , & qposmax );
@@ -265,7 +335,7 @@ static int ti_eqep_position_ceiling_write(struct counter_device *counter,
265335 struct counter_count * count ,
266336 u64 ceiling )
267337{
268- struct ti_eqep_cnt * priv = ti_eqep_count_from_counter (counter );
338+ struct ti_eqep_cnt * priv = counter_priv (counter );
269339
270340 if (ceiling != (u32 )ceiling )
271341 return - ERANGE ;
@@ -278,7 +348,7 @@ static int ti_eqep_position_ceiling_write(struct counter_device *counter,
278348static int ti_eqep_position_enable_read (struct counter_device * counter ,
279349 struct counter_count * count , u8 * enable )
280350{
281- struct ti_eqep_cnt * priv = ti_eqep_count_from_counter (counter );
351+ struct ti_eqep_cnt * priv = counter_priv (counter );
282352 u32 qepctl ;
283353
284354 regmap_read (priv -> regmap16 , QEPCTL , & qepctl );
@@ -291,7 +361,7 @@ static int ti_eqep_position_enable_read(struct counter_device *counter,
291361static int ti_eqep_position_enable_write (struct counter_device * counter ,
292362 struct counter_count * count , u8 enable )
293363{
294- struct ti_eqep_cnt * priv = ti_eqep_count_from_counter (counter );
364+ struct ti_eqep_cnt * priv = counter_priv (counter );
295365
296366 regmap_write_bits (priv -> regmap16 , QEPCTL , QEPCTL_PHEN , enable ? -1 : 0 );
297367
@@ -355,6 +425,25 @@ static struct counter_count ti_eqep_counts[] = {
355425 },
356426};
357427
428+ static irqreturn_t ti_eqep_irq_handler (int irq , void * dev_id )
429+ {
430+ struct counter_device * counter = dev_id ;
431+ struct ti_eqep_cnt * priv = counter_priv (counter );
432+ u32 qflg ;
433+
434+ regmap_read (priv -> regmap16 , QFLG , & qflg );
435+
436+ if (qflg & QFLG_PCO )
437+ counter_push_event (counter , COUNTER_EVENT_OVERFLOW , 0 );
438+
439+ if (qflg & QFLG_PCU )
440+ counter_push_event (counter , COUNTER_EVENT_UNDERFLOW , 0 );
441+
442+ regmap_write (priv -> regmap16 , QCLR , qflg );
443+
444+ return IRQ_HANDLED ;
445+ }
446+
358447static const struct regmap_config ti_eqep_regmap32_config = {
359448 .name = "32-bit" ,
360449 .reg_bits = 32 ,
@@ -378,7 +467,7 @@ static int ti_eqep_probe(struct platform_device *pdev)
378467 struct ti_eqep_cnt * priv ;
379468 void __iomem * base ;
380469 struct clk * clk ;
381- int err ;
470+ int err , irq ;
382471
383472 counter = devm_counter_alloc (dev , sizeof (* priv ));
384473 if (!counter )
@@ -399,6 +488,15 @@ static int ti_eqep_probe(struct platform_device *pdev)
399488 if (IS_ERR (priv -> regmap16 ))
400489 return PTR_ERR (priv -> regmap16 );
401490
491+ irq = platform_get_irq (pdev , 0 );
492+ if (irq < 0 )
493+ return irq ;
494+
495+ err = devm_request_threaded_irq (dev , irq , NULL , ti_eqep_irq_handler ,
496+ IRQF_ONESHOT , dev_name (dev ), counter );
497+ if (err < 0 )
498+ return dev_err_probe (dev , err , "failed to request IRQ\n" );
499+
402500 counter -> name = dev_name (dev );
403501 counter -> parent = dev ;
404502 counter -> ops = & ti_eqep_counter_ops ;
@@ -443,6 +541,7 @@ static void ti_eqep_remove(struct platform_device *pdev)
443541
444542static const struct of_device_id ti_eqep_of_match [] = {
445543 { .compatible = "ti,am3352-eqep" , },
544+ { .compatible = "ti,am62-eqep" , },
446545 { },
447546};
448547MODULE_DEVICE_TABLE (of , ti_eqep_of_match );
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