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drm/i915/gen11: Wa_1408615072/Wa_1407596294 should be on GT list
The UNSLICE_UNIT_LEVEL_CLKGATE register programmed by this workaround has 'BUS' style reset, indicating that it does not lose its value on engine resets. Furthermore, this register is part of the GT forcewake domain rather than the RENDER domain, so it should not be impacted by RCS engine resets. As such, we should implement this on the GT workaround list rather than an engine list. Bspec: 19219 Fixes: 3551ff9 ("drm/i915/gen11: Moving WAs to rcs_engine_wa_init()") Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Gustavo Sousa <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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drivers/gpu/drm/i915/gt/intel_workarounds.c

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1405,6 +1405,13 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
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GAMT_CHKN_BIT_REG,
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GAMT_CHKN_DISABLE_L3_COH_PIPE);
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1408+
/*
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* Wa_1408615072:icl,ehl (vsunit)
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* Wa_1407596294:icl,ehl (hsunit)
1411+
*/
1412+
wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
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VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);
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/* Wa_1407352427:icl,ehl */
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wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
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PSDUNIT_CLKGATE_DIS);
@@ -2614,13 +2621,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS,
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GEN11_ENABLE_32_PLANE_MODE);
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2617-
/*
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* Wa_1408615072:icl,ehl (vsunit)
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* Wa_1407596294:icl,ehl (hsunit)
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*/
2621-
wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
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VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);
2623-
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/*
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* Wa_1408767742:icl[a2..forever],ehl[all]
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* Wa_1605460711:icl[a0..c0]

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