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clk: samsung: fsd: Add initial clock support
Add initial clock support for FSD (Full Self-Driving) SoC which is required to bring-up platforms based on this SoC. Cc: [email protected] Signed-off-by: Jayati Sahu <[email protected]> Signed-off-by: Ajay Kumar <[email protected]> Signed-off-by: Pankaj Dubey <[email protected]> Signed-off-by: Alim Akhtar <[email protected]> Acked-by: Sylwester Nawrocki <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
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‎drivers/clk/samsung/Kconfig‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@ config COMMON_CLK_SAMSUNG
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select EXYNOS_5410_COMMON_CLK if ARM && SOC_EXYNOS5410
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select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420
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select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
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select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD
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config S3C64XX_COMMON_CLK
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bool "Samsung S3C64xx clock controller support" if COMPILE_TEST
@@ -124,3 +125,10 @@ config S3C2443_COMMON_CLK
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help
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Support for the clock controller present on the Samsung
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S3C2416/S3C2443 SoCs. Choose Y here only if you build for this SoC.
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config TESLA_FSD_COMMON_CLK
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bool "Tesla FSD clock controller support" if COMPILE_TEST
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depends on COMMON_CLK_SAMSUNG
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help
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Support for the clock controller present on the Tesla FSD SoC.
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Choose Y here only if you build for this SoC.

‎drivers/clk/samsung/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,3 +26,4 @@ obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
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obj-$(CONFIG_S3C2443_COMMON_CLK)+= clk-s3c2443.o
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obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o
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obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o
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obj-$(CONFIG_TESLA_FSD_COMMON_CLK) += clk-fsd.o

‎drivers/clk/samsung/clk-fsd.c‎

Lines changed: 310 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,310 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
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* https://www.samsung.com
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* Copyright (c) 2017-2022 Tesla, Inc.
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* https://www.tesla.com
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*
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* Common Clock Framework support for FSD SoC.
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*/
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#include <linux/clk-provider.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <dt-bindings/clock/fsd-clk.h>
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#include "clk.h"
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/* Register Offset definitions for CMU_CMU (0x11c10000) */
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#define PLL_LOCKTIME_PLL_SHARED0 0x0
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#define PLL_LOCKTIME_PLL_SHARED1 0x4
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#define PLL_LOCKTIME_PLL_SHARED2 0x8
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#define PLL_LOCKTIME_PLL_SHARED3 0xc
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#define PLL_CON0_PLL_SHARED0 0x100
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#define PLL_CON0_PLL_SHARED1 0x120
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#define PLL_CON0_PLL_SHARED2 0x140
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#define PLL_CON0_PLL_SHARED3 0x160
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#define MUX_CMU_CIS0_CLKMUX 0x1000
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#define MUX_CMU_CIS1_CLKMUX 0x1004
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#define MUX_CMU_CIS2_CLKMUX 0x1008
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#define MUX_CMU_CPUCL_SWITCHMUX 0x100c
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#define MUX_CMU_FSYS1_ACLK_MUX 0x1014
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#define MUX_PLL_SHARED0_MUX 0x1020
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#define MUX_PLL_SHARED1_MUX 0x1024
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#define DIV_CMU_CIS0_CLK 0x1800
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#define DIV_CMU_CIS1_CLK 0x1804
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#define DIV_CMU_CIS2_CLK 0x1808
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#define DIV_CMU_CMU_ACLK 0x180c
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#define DIV_CMU_CPUCL_SWITCH 0x1810
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#define DIV_CMU_FSYS0_SHARED0DIV4 0x181c
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#define DIV_CMU_FSYS0_SHARED1DIV3 0x1820
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#define DIV_CMU_FSYS0_SHARED1DIV4 0x1824
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#define DIV_CMU_FSYS1_SHARED0DIV4 0x1828
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#define DIV_CMU_FSYS1_SHARED0DIV8 0x182c
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#define DIV_CMU_IMEM_ACLK 0x1834
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#define DIV_CMU_IMEM_DMACLK 0x1838
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#define DIV_CMU_IMEM_TCUCLK 0x183c
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#define DIV_CMU_PERIC_SHARED0DIV20 0x1844
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#define DIV_CMU_PERIC_SHARED0DIV3_TBUCLK 0x1848
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#define DIV_CMU_PERIC_SHARED1DIV36 0x184c
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#define DIV_CMU_PERIC_SHARED1DIV4_DMACLK 0x1850
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#define DIV_PLL_SHARED0_DIV2 0x1858
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#define DIV_PLL_SHARED0_DIV3 0x185c
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#define DIV_PLL_SHARED0_DIV4 0x1860
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#define DIV_PLL_SHARED0_DIV6 0x1864
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#define DIV_PLL_SHARED1_DIV3 0x1868
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#define DIV_PLL_SHARED1_DIV36 0x186c
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#define DIV_PLL_SHARED1_DIV4 0x1870
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#define DIV_PLL_SHARED1_DIV9 0x1874
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#define GAT_CMU_CIS0_CLKGATE 0x2000
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#define GAT_CMU_CIS1_CLKGATE 0x2004
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#define GAT_CMU_CIS2_CLKGATE 0x2008
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#define GAT_CMU_CPUCL_SWITCH_GATE 0x200c
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#define GAT_CMU_FSYS0_SHARED0DIV4_GATE 0x2018
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#define GAT_CMU_FSYS0_SHARED1DIV4_CLK 0x201c
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#define GAT_CMU_FSYS0_SHARED1DIV4_GATE 0x2020
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#define GAT_CMU_FSYS1_SHARED0DIV4_GATE 0x2024
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#define GAT_CMU_FSYS1_SHARED1DIV4_GATE 0x2028
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#define GAT_CMU_IMEM_ACLK_GATE 0x2030
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#define GAT_CMU_IMEM_DMACLK_GATE 0x2034
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#define GAT_CMU_IMEM_TCUCLK_GATE 0x2038
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#define GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE 0x2040
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#define GAT_CMU_PERIC_SHARED0DIVE4_GATE 0x2044
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#define GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE 0x2048
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#define GAT_CMU_PERIC_SHARED1DIVE4_GATE 0x204c
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#define GAT_CMU_CMU_CMU_IPCLKPORT_PCLK 0x2054
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#define GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK 0x2058
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#define GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU 0x205c
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#define GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK 0x2060
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static const unsigned long cmu_clk_regs[] __initconst = {
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PLL_LOCKTIME_PLL_SHARED0,
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PLL_LOCKTIME_PLL_SHARED1,
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PLL_LOCKTIME_PLL_SHARED2,
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PLL_LOCKTIME_PLL_SHARED3,
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PLL_CON0_PLL_SHARED0,
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PLL_CON0_PLL_SHARED1,
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PLL_CON0_PLL_SHARED2,
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PLL_CON0_PLL_SHARED3,
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MUX_CMU_CIS0_CLKMUX,
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MUX_CMU_CIS1_CLKMUX,
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MUX_CMU_CIS2_CLKMUX,
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MUX_CMU_CPUCL_SWITCHMUX,
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MUX_CMU_FSYS1_ACLK_MUX,
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MUX_PLL_SHARED0_MUX,
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MUX_PLL_SHARED1_MUX,
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DIV_CMU_CIS0_CLK,
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DIV_CMU_CIS1_CLK,
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DIV_CMU_CIS2_CLK,
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DIV_CMU_CMU_ACLK,
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DIV_CMU_CPUCL_SWITCH,
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DIV_CMU_FSYS0_SHARED0DIV4,
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DIV_CMU_FSYS0_SHARED1DIV3,
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DIV_CMU_FSYS0_SHARED1DIV4,
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DIV_CMU_FSYS1_SHARED0DIV4,
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DIV_CMU_FSYS1_SHARED0DIV8,
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DIV_CMU_IMEM_ACLK,
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DIV_CMU_IMEM_DMACLK,
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DIV_CMU_IMEM_TCUCLK,
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DIV_CMU_PERIC_SHARED0DIV20,
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DIV_CMU_PERIC_SHARED0DIV3_TBUCLK,
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DIV_CMU_PERIC_SHARED1DIV36,
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DIV_CMU_PERIC_SHARED1DIV4_DMACLK,
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DIV_PLL_SHARED0_DIV2,
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DIV_PLL_SHARED0_DIV3,
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DIV_PLL_SHARED0_DIV4,
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DIV_PLL_SHARED0_DIV6,
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DIV_PLL_SHARED1_DIV3,
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DIV_PLL_SHARED1_DIV36,
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DIV_PLL_SHARED1_DIV4,
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DIV_PLL_SHARED1_DIV9,
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GAT_CMU_CIS0_CLKGATE,
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GAT_CMU_CIS1_CLKGATE,
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GAT_CMU_CIS2_CLKGATE,
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GAT_CMU_CPUCL_SWITCH_GATE,
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GAT_CMU_FSYS0_SHARED0DIV4_GATE,
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GAT_CMU_FSYS0_SHARED1DIV4_CLK,
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GAT_CMU_FSYS0_SHARED1DIV4_GATE,
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GAT_CMU_FSYS1_SHARED0DIV4_GATE,
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GAT_CMU_FSYS1_SHARED1DIV4_GATE,
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GAT_CMU_IMEM_ACLK_GATE,
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GAT_CMU_IMEM_DMACLK_GATE,
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GAT_CMU_IMEM_TCUCLK_GATE,
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GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE,
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GAT_CMU_PERIC_SHARED0DIVE4_GATE,
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GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE,
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GAT_CMU_PERIC_SHARED1DIVE4_GATE,
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GAT_CMU_CMU_CMU_IPCLKPORT_PCLK,
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GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK,
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GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU,
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GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK,
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};
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static const struct samsung_pll_rate_table pll_shared0_rate_table[] __initconst = {
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PLL_35XX_RATE(24 * MHZ, 2000000000U, 250, 3, 0),
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};
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static const struct samsung_pll_rate_table pll_shared1_rate_table[] __initconst = {
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PLL_35XX_RATE(24 * MHZ, 2400000000U, 200, 2, 0),
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};
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static const struct samsung_pll_rate_table pll_shared2_rate_table[] __initconst = {
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PLL_35XX_RATE(24 * MHZ, 2400000000U, 200, 2, 0),
155+
};
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static const struct samsung_pll_rate_table pll_shared3_rate_table[] __initconst = {
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PLL_35XX_RATE(24 * MHZ, 1800000000U, 150, 2, 0),
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};
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static const struct samsung_pll_clock cmu_pll_clks[] __initconst = {
162+
PLL(pll_142xx, 0, "fout_pll_shared0", "fin_pll", PLL_LOCKTIME_PLL_SHARED0,
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PLL_CON0_PLL_SHARED0, pll_shared0_rate_table),
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PLL(pll_142xx, 0, "fout_pll_shared1", "fin_pll", PLL_LOCKTIME_PLL_SHARED1,
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PLL_CON0_PLL_SHARED1, pll_shared1_rate_table),
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PLL(pll_142xx, 0, "fout_pll_shared2", "fin_pll", PLL_LOCKTIME_PLL_SHARED2,
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PLL_CON0_PLL_SHARED2, pll_shared2_rate_table),
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PLL(pll_142xx, 0, "fout_pll_shared3", "fin_pll", PLL_LOCKTIME_PLL_SHARED3,
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PLL_CON0_PLL_SHARED3, pll_shared3_rate_table),
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};
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/* List of parent clocks for Muxes in CMU_CMU */
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PNAME(mout_cmu_shared0_pll_p) = { "fin_pll", "fout_pll_shared0" };
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PNAME(mout_cmu_shared1_pll_p) = { "fin_pll", "fout_pll_shared1" };
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PNAME(mout_cmu_shared2_pll_p) = { "fin_pll", "fout_pll_shared2" };
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PNAME(mout_cmu_shared3_pll_p) = { "fin_pll", "fout_pll_shared3" };
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PNAME(mout_cmu_cis0_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
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PNAME(mout_cmu_cis1_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
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PNAME(mout_cmu_cis2_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
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PNAME(mout_cmu_cpucl_switchmux_p) = { "mout_cmu_pll_shared2", "mout_cmu_pll_shared0_mux" };
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PNAME(mout_cmu_fsys1_aclk_mux_p) = { "dout_cmu_pll_shared0_div4", "fin_pll" };
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PNAME(mout_cmu_pll_shared0_mux_p) = { "fin_pll", "mout_cmu_pll_shared0" };
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PNAME(mout_cmu_pll_shared1_mux_p) = { "fin_pll", "mout_cmu_pll_shared1" };
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static const struct samsung_mux_clock cmu_mux_clks[] __initconst = {
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MUX(0, "mout_cmu_pll_shared0", mout_cmu_shared0_pll_p, PLL_CON0_PLL_SHARED0, 4, 1),
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MUX(0, "mout_cmu_pll_shared1", mout_cmu_shared1_pll_p, PLL_CON0_PLL_SHARED1, 4, 1),
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MUX(0, "mout_cmu_pll_shared2", mout_cmu_shared2_pll_p, PLL_CON0_PLL_SHARED2, 4, 1),
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MUX(0, "mout_cmu_pll_shared3", mout_cmu_shared3_pll_p, PLL_CON0_PLL_SHARED3, 4, 1),
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MUX(0, "mout_cmu_cis0_clkmux", mout_cmu_cis0_clkmux_p, MUX_CMU_CIS0_CLKMUX, 0, 1),
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MUX(0, "mout_cmu_cis1_clkmux", mout_cmu_cis1_clkmux_p, MUX_CMU_CIS1_CLKMUX, 0, 1),
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MUX(0, "mout_cmu_cis2_clkmux", mout_cmu_cis2_clkmux_p, MUX_CMU_CIS2_CLKMUX, 0, 1),
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MUX(0, "mout_cmu_cpucl_switchmux", mout_cmu_cpucl_switchmux_p,
194+
MUX_CMU_CPUCL_SWITCHMUX, 0, 1),
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MUX(0, "mout_cmu_fsys1_aclk_mux", mout_cmu_fsys1_aclk_mux_p, MUX_CMU_FSYS1_ACLK_MUX, 0, 1),
196+
MUX(0, "mout_cmu_pll_shared0_mux", mout_cmu_pll_shared0_mux_p, MUX_PLL_SHARED0_MUX, 0, 1),
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MUX(0, "mout_cmu_pll_shared1_mux", mout_cmu_pll_shared1_mux_p, MUX_PLL_SHARED1_MUX, 0, 1),
198+
};
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static const struct samsung_div_clock cmu_div_clks[] __initconst = {
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DIV(0, "dout_cmu_cis0_clk", "cmu_cis0_clkgate", DIV_CMU_CIS0_CLK, 0, 4),
202+
DIV(0, "dout_cmu_cis1_clk", "cmu_cis1_clkgate", DIV_CMU_CIS1_CLK, 0, 4),
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DIV(0, "dout_cmu_cis2_clk", "cmu_cis2_clkgate", DIV_CMU_CIS2_CLK, 0, 4),
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DIV(0, "dout_cmu_cmu_aclk", "dout_cmu_pll_shared1_div9", DIV_CMU_CMU_ACLK, 0, 4),
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DIV(0, "dout_cmu_cpucl_switch", "cmu_cpucl_switch_gate", DIV_CMU_CPUCL_SWITCH, 0, 4),
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DIV(DOUT_CMU_FSYS0_SHARED0DIV4, "dout_cmu_fsys0_shared0div4", "cmu_fsys0_shared0div4_gate",
207+
DIV_CMU_FSYS0_SHARED0DIV4, 0, 4),
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DIV(0, "dout_cmu_fsys0_shared1div3", "cmu_fsys0_shared1div4_clk",
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DIV_CMU_FSYS0_SHARED1DIV3, 0, 4),
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DIV(DOUT_CMU_FSYS0_SHARED1DIV4, "dout_cmu_fsys0_shared1div4", "cmu_fsys0_shared1div4_gate",
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DIV_CMU_FSYS0_SHARED1DIV4, 0, 4),
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DIV(DOUT_CMU_FSYS1_SHARED0DIV4, "dout_cmu_fsys1_shared0div4", "cmu_fsys1_shared0div4_gate",
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DIV_CMU_FSYS1_SHARED0DIV4, 0, 4),
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DIV(DOUT_CMU_FSYS1_SHARED0DIV8, "dout_cmu_fsys1_shared0div8", "cmu_fsys1_shared1div4_gate",
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DIV_CMU_FSYS1_SHARED0DIV8, 0, 4),
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DIV(DOUT_CMU_IMEM_ACLK, "dout_cmu_imem_aclk", "cmu_imem_aclk_gate",
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DIV_CMU_IMEM_ACLK, 0, 4),
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DIV(DOUT_CMU_IMEM_DMACLK, "dout_cmu_imem_dmaclk", "cmu_imem_dmaclk_gate",
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DIV_CMU_IMEM_DMACLK, 0, 4),
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DIV(DOUT_CMU_IMEM_TCUCLK, "dout_cmu_imem_tcuclk", "cmu_imem_tcuclk_gate",
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DIV_CMU_IMEM_TCUCLK, 0, 4),
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DIV(DOUT_CMU_PERIC_SHARED0DIV20, "dout_cmu_peric_shared0div20",
223+
"cmu_peric_shared0dive4_gate", DIV_CMU_PERIC_SHARED0DIV20, 0, 4),
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DIV(DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK, "dout_cmu_peric_shared0div3_tbuclk",
225+
"cmu_peric_shared0dive3_tbuclk_gate", DIV_CMU_PERIC_SHARED0DIV3_TBUCLK, 0, 4),
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DIV(DOUT_CMU_PERIC_SHARED1DIV36, "dout_cmu_peric_shared1div36",
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"cmu_peric_shared1dive4_gate", DIV_CMU_PERIC_SHARED1DIV36, 0, 4),
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DIV(DOUT_CMU_PERIC_SHARED1DIV4_DMACLK, "dout_cmu_peric_shared1div4_dmaclk",
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"cmu_peric_shared1div4_dmaclk_gate", DIV_CMU_PERIC_SHARED1DIV4_DMACLK, 0, 4),
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DIV(0, "dout_cmu_pll_shared0_div2", "mout_cmu_pll_shared0_mux",
231+
DIV_PLL_SHARED0_DIV2, 0, 4),
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DIV(0, "dout_cmu_pll_shared0_div3", "mout_cmu_pll_shared0_mux",
233+
DIV_PLL_SHARED0_DIV3, 0, 4),
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DIV(DOUT_CMU_PLL_SHARED0_DIV4, "dout_cmu_pll_shared0_div4", "dout_cmu_pll_shared0_div2",
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DIV_PLL_SHARED0_DIV4, 0, 4),
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DIV(DOUT_CMU_PLL_SHARED0_DIV6, "dout_cmu_pll_shared0_div6", "dout_cmu_pll_shared0_div3",
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DIV_PLL_SHARED0_DIV6, 0, 4),
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DIV(0, "dout_cmu_pll_shared1_div3", "mout_cmu_pll_shared1_mux",
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DIV_PLL_SHARED1_DIV3, 0, 4),
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DIV(0, "dout_cmu_pll_shared1_div36", "dout_cmu_pll_shared1_div9",
241+
DIV_PLL_SHARED1_DIV36, 0, 4),
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DIV(0, "dout_cmu_pll_shared1_div4", "mout_cmu_pll_shared1_mux",
243+
DIV_PLL_SHARED1_DIV4, 0, 4),
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DIV(0, "dout_cmu_pll_shared1_div9", "dout_cmu_pll_shared1_div3",
245+
DIV_PLL_SHARED1_DIV9, 0, 4),
246+
};
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static const struct samsung_gate_clock cmu_gate_clks[] __initconst = {
249+
GATE(0, "cmu_cis0_clkgate", "mout_cmu_cis0_clkmux", GAT_CMU_CIS0_CLKGATE, 21,
250+
CLK_IGNORE_UNUSED, 0),
251+
GATE(0, "cmu_cis1_clkgate", "mout_cmu_cis1_clkmux", GAT_CMU_CIS1_CLKGATE, 21,
252+
CLK_IGNORE_UNUSED, 0),
253+
GATE(0, "cmu_cis2_clkgate", "mout_cmu_cis2_clkmux", GAT_CMU_CIS2_CLKGATE, 21,
254+
CLK_IGNORE_UNUSED, 0),
255+
GATE(CMU_CPUCL_SWITCH_GATE, "cmu_cpucl_switch_gate", "mout_cmu_cpucl_switchmux",
256+
GAT_CMU_CPUCL_SWITCH_GATE, 21, CLK_IGNORE_UNUSED, 0),
257+
GATE(GAT_CMU_FSYS0_SHARED0DIV4, "cmu_fsys0_shared0div4_gate", "dout_cmu_pll_shared0_div4",
258+
GAT_CMU_FSYS0_SHARED0DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
259+
GATE(0, "cmu_fsys0_shared1div4_clk", "dout_cmu_pll_shared1_div3",
260+
GAT_CMU_FSYS0_SHARED1DIV4_CLK, 21, CLK_IGNORE_UNUSED, 0),
261+
GATE(0, "cmu_fsys0_shared1div4_gate", "dout_cmu_pll_shared1_div4",
262+
GAT_CMU_FSYS0_SHARED1DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
263+
GATE(0, "cmu_fsys1_shared0div4_gate", "mout_cmu_fsys1_aclk_mux",
264+
GAT_CMU_FSYS1_SHARED0DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
265+
GATE(0, "cmu_fsys1_shared1div4_gate", "dout_cmu_fsys1_shared0div4",
266+
GAT_CMU_FSYS1_SHARED1DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
267+
GATE(0, "cmu_imem_aclk_gate", "dout_cmu_pll_shared1_div9", GAT_CMU_IMEM_ACLK_GATE, 21,
268+
CLK_IGNORE_UNUSED, 0),
269+
GATE(0, "cmu_imem_dmaclk_gate", "mout_cmu_pll_shared1_mux", GAT_CMU_IMEM_DMACLK_GATE, 21,
270+
CLK_IGNORE_UNUSED, 0),
271+
GATE(0, "cmu_imem_tcuclk_gate", "dout_cmu_pll_shared0_div3", GAT_CMU_IMEM_TCUCLK_GATE, 21,
272+
CLK_IGNORE_UNUSED, 0),
273+
GATE(0, "cmu_peric_shared0dive3_tbuclk_gate", "dout_cmu_pll_shared0_div3",
274+
GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE, 21, CLK_IGNORE_UNUSED, 0),
275+
GATE(0, "cmu_peric_shared0dive4_gate", "dout_cmu_pll_shared0_div4",
276+
GAT_CMU_PERIC_SHARED0DIVE4_GATE, 21, CLK_IGNORE_UNUSED, 0),
277+
GATE(0, "cmu_peric_shared1div4_dmaclk_gate", "dout_cmu_pll_shared1_div4",
278+
GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE, 21, CLK_IGNORE_UNUSED, 0),
279+
GATE(0, "cmu_peric_shared1dive4_gate", "dout_cmu_pll_shared1_div36",
280+
GAT_CMU_PERIC_SHARED1DIVE4_GATE, 21, CLK_IGNORE_UNUSED, 0),
281+
GATE(0, "cmu_uid_cmu_cmu_cmu_ipclkport_pclk", "dout_cmu_cmu_aclk",
282+
GAT_CMU_CMU_CMU_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
283+
GATE(0, "cmu_uid_axi2apb_cmu_ipclkport_aclk", "dout_cmu_cmu_aclk",
284+
GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
285+
GATE(0, "cmu_uid_ns_brdg_cmu_ipclkport_clk__psoc_cmu__clk_cmu", "dout_cmu_cmu_aclk",
286+
GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU, 21, CLK_IGNORE_UNUSED, 0),
287+
GATE(0, "cmu_uid_sysreg_cmu_ipclkport_pclk", "dout_cmu_cmu_aclk",
288+
GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
289+
};
290+
291+
static const struct samsung_cmu_info cmu_cmu_info __initconst = {
292+
.pll_clks = cmu_pll_clks,
293+
.nr_pll_clks = ARRAY_SIZE(cmu_pll_clks),
294+
.mux_clks = cmu_mux_clks,
295+
.nr_mux_clks = ARRAY_SIZE(cmu_mux_clks),
296+
.div_clks = cmu_div_clks,
297+
.nr_div_clks = ARRAY_SIZE(cmu_div_clks),
298+
.gate_clks = cmu_gate_clks,
299+
.nr_gate_clks = ARRAY_SIZE(cmu_gate_clks),
300+
.nr_clk_ids = CMU_NR_CLK,
301+
.clk_regs = cmu_clk_regs,
302+
.nr_clk_regs = ARRAY_SIZE(cmu_clk_regs),
303+
};
304+
305+
static void __init fsd_clk_cmu_init(struct device_node *np)
306+
{
307+
samsung_cmu_register_one(np, &cmu_cmu_info);
308+
}
309+
310+
CLK_OF_DECLARE(fsd_clk_cmu, "tesla,fsd-clock-cmu", fsd_clk_cmu_init);

‎drivers/clk/samsung/clk-pll.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1469,6 +1469,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
14691469
case pll_1450x:
14701470
case pll_1451x:
14711471
case pll_1452x:
1472+
case pll_142xx:
14721473
pll->enable_offs = PLL35XX_ENABLE_SHIFT;
14731474
pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT;
14741475
if (!pll->rate_table)

‎drivers/clk/samsung/clk-pll.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@ enum samsung_pll_type {
3939
pll_1460x,
4040
pll_0822x,
4141
pll_0831x,
42+
pll_142xx,
4243
};
4344

4445
#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \

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