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| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/clock/tesla,fsd-clock.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: Tesla FSD (Full Self-Driving) SoC clock controller |
| 8 | + |
| 9 | +maintainers: |
| 10 | + |
| 11 | + |
| 12 | + |
| 13 | +description: | |
| 14 | + FSD clock controller consist of several clock management unit |
| 15 | + (CMU), which generates clocks for various inteernal SoC blocks. |
| 16 | + The root clock comes from external OSC clock (24 MHz). |
| 17 | +
|
| 18 | + All available clocks are defined as preprocessor macros in |
| 19 | + 'dt-bindings/clock/fsd-clk.h' header. |
| 20 | +
|
| 21 | +properties: |
| 22 | + compatible: |
| 23 | + enum: |
| 24 | + - tesla,fsd-clock-cmu |
| 25 | + - tesla,fsd-clock-imem |
| 26 | + - tesla,fsd-clock-peric |
| 27 | + - tesla,fsd-clock-fsys0 |
| 28 | + - tesla,fsd-clock-fsys1 |
| 29 | + - tesla,fsd-clock-mfc |
| 30 | + - tesla,fsd-clock-cam_csi |
| 31 | + |
| 32 | + clocks: |
| 33 | + minItems: 1 |
| 34 | + maxItems: 6 |
| 35 | + |
| 36 | + clock-names: |
| 37 | + minItems: 1 |
| 38 | + maxItems: 6 |
| 39 | + |
| 40 | + "#clock-cells": |
| 41 | + const: 1 |
| 42 | + |
| 43 | + reg: |
| 44 | + maxItems: 1 |
| 45 | + |
| 46 | +allOf: |
| 47 | + - if: |
| 48 | + properties: |
| 49 | + compatible: |
| 50 | + contains: |
| 51 | + const: tesla,fsd-clock-cmu |
| 52 | + then: |
| 53 | + properties: |
| 54 | + clocks: |
| 55 | + items: |
| 56 | + - description: External reference clock (24 MHz) |
| 57 | + clock-names: |
| 58 | + items: |
| 59 | + - const: fin_pll |
| 60 | + |
| 61 | + - if: |
| 62 | + properties: |
| 63 | + compatible: |
| 64 | + contains: |
| 65 | + const: tesla,fsd-clock-imem |
| 66 | + then: |
| 67 | + properties: |
| 68 | + clocks: |
| 69 | + items: |
| 70 | + - description: External reference clock (24 MHz) |
| 71 | + - description: IMEM TCU clock (from CMU_CMU) |
| 72 | + - description: IMEM bus clock (from CMU_CMU) |
| 73 | + - description: IMEM DMA clock (from CMU_CMU) |
| 74 | + clock-names: |
| 75 | + items: |
| 76 | + - const: fin_pll |
| 77 | + - const: dout_cmu_imem_tcuclk |
| 78 | + - const: dout_cmu_imem_aclk |
| 79 | + - const: dout_cmu_imem_dmaclk |
| 80 | + |
| 81 | + - if: |
| 82 | + properties: |
| 83 | + compatible: |
| 84 | + contains: |
| 85 | + const: tesla,fsd-clock-peric |
| 86 | + then: |
| 87 | + properties: |
| 88 | + clocks: |
| 89 | + items: |
| 90 | + - description: External reference clock (24 MHz) |
| 91 | + - description: Shared0 PLL div4 clock (from CMU_CMU) |
| 92 | + - description: PERIC shared1 div36 clock (from CMU_CMU) |
| 93 | + - description: PERIC shared0 div3 TBU clock (from CMU_CMU) |
| 94 | + - description: PERIC shared0 div20 clock (from CMU_CMU) |
| 95 | + - description: PERIC shared1 div4 DMAclock (from CMU_CMU) |
| 96 | + clock-names: |
| 97 | + items: |
| 98 | + - const: fin_pll |
| 99 | + - const: dout_cmu_pll_shared0_div4 |
| 100 | + - const: dout_cmu_peric_shared1div36 |
| 101 | + - const: dout_cmu_peric_shared0div3_tbuclk |
| 102 | + - const: dout_cmu_peric_shared0div20 |
| 103 | + - const: dout_cmu_peric_shared1div4_dmaclk |
| 104 | + |
| 105 | + - if: |
| 106 | + properties: |
| 107 | + compatible: |
| 108 | + contains: |
| 109 | + const: tesla,fsd-clock-fsys0 |
| 110 | + then: |
| 111 | + properties: |
| 112 | + clocks: |
| 113 | + items: |
| 114 | + - description: External reference clock (24 MHz) |
| 115 | + - description: Shared0 PLL div6 clock (from CMU_CMU) |
| 116 | + - description: FSYS0 shared1 div4 clock (from CMU_CMU) |
| 117 | + - description: FSYS0 shared0 div4 clock (from CMU_CMU) |
| 118 | + clock-names: |
| 119 | + items: |
| 120 | + - const: fin_pll |
| 121 | + - const: dout_cmu_pll_shared0_div6 |
| 122 | + - const: dout_cmu_fsys0_shared1div4 |
| 123 | + - const: dout_cmu_fsys0_shared0div4 |
| 124 | + |
| 125 | + - if: |
| 126 | + properties: |
| 127 | + compatible: |
| 128 | + contains: |
| 129 | + const: tesla,fsd-clock-fsys1 |
| 130 | + then: |
| 131 | + properties: |
| 132 | + clocks: |
| 133 | + items: |
| 134 | + - description: External reference clock (24 MHz) |
| 135 | + - description: FSYS1 shared0 div8 clock (from CMU_CMU) |
| 136 | + - description: FSYS1 shared0 div4 clock (from CMU_CMU) |
| 137 | + clock-names: |
| 138 | + items: |
| 139 | + - const: fin_pll |
| 140 | + - const: dout_cmu_fsys1_shared0div8 |
| 141 | + - const: dout_cmu_fsys1_shared0div4 |
| 142 | + |
| 143 | + - if: |
| 144 | + properties: |
| 145 | + compatible: |
| 146 | + contains: |
| 147 | + const: tesla,fsd-clock-mfc |
| 148 | + then: |
| 149 | + properties: |
| 150 | + clocks: |
| 151 | + items: |
| 152 | + - description: External reference clock (24 MHz) |
| 153 | + clock-names: |
| 154 | + items: |
| 155 | + - const: fin_pll |
| 156 | + |
| 157 | + - if: |
| 158 | + properties: |
| 159 | + compatible: |
| 160 | + contains: |
| 161 | + const: tesla,fsd-clock-cam_csi |
| 162 | + then: |
| 163 | + properties: |
| 164 | + clocks: |
| 165 | + items: |
| 166 | + - description: External reference clock (24 MHz) |
| 167 | + clock-names: |
| 168 | + items: |
| 169 | + - const: fin_pll |
| 170 | + |
| 171 | +required: |
| 172 | + - compatible |
| 173 | + - "#clock-cells" |
| 174 | + - clocks |
| 175 | + - clock-names |
| 176 | + - reg |
| 177 | + |
| 178 | +additionalProperties: false |
| 179 | + |
| 180 | +examples: |
| 181 | + # Clock controller node for CMU_FSYS1 |
| 182 | + - | |
| 183 | + #include <dt-bindings/clock/fsd-clk.h> |
| 184 | +
|
| 185 | + clock_fsys1: clock-controller@16810000 { |
| 186 | + compatible = "tesla,fsd-clock-fsys1"; |
| 187 | + reg = <0x16810000 0x3000>; |
| 188 | + #clock-cells = <1>; |
| 189 | +
|
| 190 | + clocks = <&fin_pll>, |
| 191 | + <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>, |
| 192 | + <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>; |
| 193 | + clock-names = "fin_pll", |
| 194 | + "dout_cmu_fsys1_shared0div8", |
| 195 | + "dout_cmu_fsys1_shared0div4"; |
| 196 | + }; |
| 197 | +
|
| 198 | +... |
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