Revision 0 errata

One peculiarity of the original Disk II is that the layout of the address and data pins of the P5 ROM (which contains the firmware code) do not match the nominal pin ordering as shown in the 6309 datasheet. This means that if you pull the chip and dump it as a "standard" 6309 you won't get valid 6502 code, it will be scrambled. Some of the dumps found out on the internet are scrambled in this manner, while some are dumped as proper code. (These ones are proper code.)

While converting the Disk II circuit to use an EPROM (or EEPROM) to hold the firmware instead, I designed it to use the EPROMs nominal pin ordering. Therefore it needs the proper, unscrambled, P5 firmware burnt to it.

Unfortunately my conversion also left some of the routing in a broken state, namely the connection of the data bus between P5 and the 74LS323 shift register. In order to make revision 0 of my card work, you must cut all 8 data lines going to the '323 and reconnect them in the correct order.

Cut all 8 lines as shown here on the back of the card:

And reconnect all 8 of the data lines by soldering short bodge wires: