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Currently Extension for Verilog Language file on master branch is wrong

So Updated Verilog Language File extension in file-extension.json

"Verilog": [".veo"] to "Verilog": [".v",".vh",".vlg"]

Reference : https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/reference/glossary/def_v.htm#:~:text=v%2C%20.,any%20other%20standard%20text%20editor.

https://en.wikipedia.org/wiki/Verilog

@vishalkatigar
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@loubnabnl, @liyongsea @lingjzhu , Please review and merge if you think this is ok

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