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Jan 25, 2019
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Devkit 1.4.6. updates[do not use] #448

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d9a8199
Devkit 1.4.6. updates
AWSaalluri Jan 20, 2019
b4425cc
updating permissions to be able to execute
AWSaalluri Jan 21, 2019
f780bd9
fixing merge issues
AWSaalluri Jan 21, 2019
3b2d9c3
RC_v1_4_6 delta updates & release notes
AWSaalluri Jan 22, 2019
132c3ac
updating with table of supported simulator versions
AWSaalluri Jan 23, 2019
dd40d5e
Update RTL_Simulating_CL_Designs.md
AWSaalluri Jan 23, 2019
fa251de
Update FAQs.md
AWSaalluri Jan 23, 2019
83b1b7f
updating public afi for cl_dram_dma
AWSaalluri Jan 24, 2019
2b4e85c
Update RELEASE_NOTES.md
AWSaalluri Jan 24, 2019
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11 changes: 3 additions & 8 deletions FAQs.md
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Expand Up @@ -460,14 +460,9 @@ Parent process (pid 8160) has died. This helper process will now exit

You would need a valid [on premise license](./hdk/docs/on_premise_licensing_help.md) provided by Xilinx.

*For runs using the FPGA Developer AMI:*

**NOTE:**
> * The license included on FPGA Developer AMI Versions 1.3.0_a and earlier expires on October 31 2017.
> * If you see the above error, please update to FPGA Developer AMI Version 1.3.3 or later.
> * All FPGA Developer AMI Versions 1.3.0_a and earlier will be deprecated once Version 1.3.3 is released.
> * If you are using the FPGA Developer AMI Version 1.3.3 or later, please check if the environment variable `XILINXD_LICENSE_FILE` is set to `/opt/Xilinx/license/XilinxAWS.lic`
> * If you still face the above error, please contact us on the forums and we'd be happy to help further.
*For runs using the FPGA Developer AMI:* Please contact us through [AWS FPGA Developers forum](https://forums.aws.amazon.com/forum.jspa?forumID=243)



**Q: Why does Vivado in GUI mode show up blank ? or Why does Vivado in GUI mode show up as an empty window?**

Expand Down
114 changes: 98 additions & 16 deletions Jenkinsfile
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Expand Up @@ -11,6 +11,7 @@ properties([parameters([
booleanParam(name: 'test_hdk_scripts', defaultValue: true, description: 'Test the HDK setup scripts'),
booleanParam(name: 'test_sims', defaultValue: true, description: 'Run all Simulations'),
booleanParam(name: 'test_edma', defaultValue: true, description: 'Run EDMA unit and perf tests'),
booleanParam(name: 'test_non_root_access', defaultValue: true, description: 'Test non-root access to FPGA tools'),
booleanParam(name: 'test_xdma', defaultValue: true, description: 'Test XDMA driver'),
booleanParam(name: 'test_runtime_software', defaultValue: true, description: 'Test precompiled AFIs'),
booleanParam(name: 'test_dcp_recipes', defaultValue: false, description: 'Run DCP generation with all clock recipes and build strategies.'),
Expand All @@ -22,8 +23,8 @@ properties([parameters([
booleanParam(name: 'debug_fdf_uram', defaultValue: false, description: 'Debug the FDF for cl_uram_example.'),
booleanParam(name: 'fdf_ddr_comb', defaultValue: false, description: 'run FDF for cl_dram_dma ddr combinations.'),
booleanParam(name: 'disable_runtime_tests', defaultValue: false, description: 'Option to disable runtime tests.'),
booleanParam(name: 'use_test_ami', defaultValue: false, description: 'This option asks for the test AMI from Jenkins')

booleanParam(name: 'use_test_ami', defaultValue: false, description: 'This option asks for the test AMI from Jenkins'),
booleanParam(name: 'internal_simulations', defaultValue: false, description: 'This option asks for default agent from Jenkins')
])])

//=============================================================================
Expand All @@ -35,6 +36,7 @@ boolean test_hdk_scripts = params.get('test_hdk_scripts')
boolean test_fpga_tools = params.get('test_fpga_tools')
boolean test_sims = params.get('test_sims')
boolean test_edma = params.get('test_edma')
boolean test_non_root_access = params.get('test_non_root_access')
boolean test_xdma = params.get('test_xdma')
boolean test_runtime_software = params.get('test_runtime_software')
boolean test_dcp_recipes = params.get('test_dcp_recipes')
Expand Down Expand Up @@ -102,14 +104,14 @@ def all_tests = [:]
// Task to Label map
task_label = [
'create_afi': 't2.l_50',
'simulation': 'c4.xl',
'dcp_gen': 'c4.4xl',
'simulation': 'z1d.l',
'dcp_gen': 'z1d.2xl',
'runtime': 'f1.2xl',
'runtime_all_slots': 'f1.16xl',
'source_scripts': 'c4.xl',
'md_links': 'c4.xl',
'find_tests': 't2.l_50',
'sdaccel_builds': 'c4.4xl'
'sdaccel_builds': 'z1d.2xl'
]

def xilinx_versions = [ '2017.4', '2018.2' ]
Expand All @@ -133,6 +135,19 @@ def sdaccel_example_default_map = [ '2017.4' : [ 'Hello_World_1ddr': 'SDAccel/ex
]
]

def simulator_tool_default_map = [ '2017.4' : [ 'vivado': 'xilinx/SDx/2017.4_04112018',
'vcs': 'vcs-mx/L-2016.06-1',
'questa': 'questa/10.6b',
'ies': 'incisive/15.20.063'
],
'2018.2' : [ 'vivado': 'xilinx/SDx/2018.2_06142018',
'vcs': 'vcs-mx/N-2017.12-SP1-1',
'questa': 'questa/10.6c_1',
'ies': 'incisive/15.20.063'
]
]


// Get serializable entry set
@NonCPS def entrySet(m) {m.collect {k, v -> [key: k, value: v]}}

Expand All @@ -150,6 +165,10 @@ def get_task_label(Map args=[ : ]) {
echo "Test AMI Requested"
task_label = task_label + '_test'
}
if (params.internal_simulations) {
echo "internal simulation agent requested"
task_label = 'f1'
}

echo "Label Requested: $task_label"
return task_label
Expand Down Expand Up @@ -341,27 +360,56 @@ if (test_fpga_tools) {
}
}


if (test_sims) {
all_tests['Run Sims'] = {
stage('Run Sims') {
def cl_names = ['cl_uram_example', 'cl_dram_dma', 'cl_hello_world']
def simulators = ['vivado']
def sim_nodes = [:]
if(params.internal_simulations) {
simulators = ['vcs', 'ies', 'questa', 'vivado']
}
for (x in cl_names) {
for (y in xilinx_versions) {
String xilinx_version = y
String cl_name = x
String node_name = "Sim ${cl_name} ${xilinx_version}"
String key = "test_${cl_name}__"
String report_file = "test_sims_${cl_name}_${xilinx_version}.xml"
sim_nodes[node_name] = {
for ( z in simulators) {
String xilinx_version = y
String cl_name = x
String simulator = z
String node_name = "Sim ${cl_name} ${xilinx_version}"
String key = "test_${cl_name}__"
String report_file = "test_sims_${cl_name}_${xilinx_version}.xml"
def tool_module_map = simulator_tool_default_map.get(xilinx_version)
String vcs_module = tool_module_map.get('vcs')
String questa_module = tool_module_map.get('questa')
String ies_module = tool_module_map.get('ies')
String vivado_module = tool_module_map.get('vivado')
if(params.internal_simulations) {
report_file = "test_sims_${cl_name}_${xilinx_version}_${simulator}.xml"
}
sim_nodes[node_name] = {
node(get_task_label(task: 'simulation', xilinx_version: xilinx_version)) {
checkout scm
try {
sh """
set -e
source $WORKSPACE/shared/tests/bin/setup_test_hdk_env.sh
python2.7 -m pytest -v $WORKSPACE/hdk/tests/simulation_tests/test_sims.py -k \"${key}\" --junit-xml $WORKSPACE/${report_file}
"""
if(params.internal_simulations) {
sh """
set -e
module purge
module load python/2.7.9
module load ${vivado_module}
module load ${vcs_module}
module load ${questa_module}
module load ${ies_module}
source $WORKSPACE/hdk_setup.sh
python2.7 -m pytest -v $WORKSPACE/hdk/tests/simulation_tests/test_sims.py -k \"${key}\" --junit-xml $WORKSPACE/${report_file} --Simulator ${simulator}
"""
} else {
sh """
set -e
source $WORKSPACE/shared/tests/bin/setup_test_hdk_env.sh
python2.7 -m pytest -v $WORKSPACE/hdk/tests/simulation_tests/test_sims.py -k \"${key}\" --junit-xml $WORKSPACE/${report_file} --Simulator ${simulator}
"""
}
} catch (exc) {
echo "${node_name} failed: archiving results"
archiveArtifacts artifacts: "hdk/cl/examples/${cl_name}/verif/sim/**", fingerprint: true
Expand All @@ -377,6 +425,7 @@ if (test_sims) {
}
}
}
}
}
parallel sim_nodes
}
Expand Down Expand Up @@ -420,6 +469,39 @@ if (test_edma) {
}
}

if (test_non_root_access) {
all_tests['Test non-root access to FPGA tools'] = {
stage('Test non-root access to FPGA tools') {
node(get_task_label(task: 'runtime', xilinx_version: default_xilinx_version)) {

echo "Test non-root access to FPGA tools"
checkout scm

String test = "sdk/tests/test_non_root_access.py"
String report_file = "test_non_root_access.xml"

try {
sh """
export AWS_FPGA_ALLOW_NON_ROOT=y
export AWS_FPGA_SDK_OVERRIDE_GROUP=y
set -e
source $WORKSPACE/shared/tests/bin/setup_test_sdk_env.sh
newgrp fpgauser
export SDK_DIR="${WORKSPACE}/sdk"
source $WORKSPACE/shared/tests/bin/setup_test_env.sh
python2.7 -m pytest -v $WORKSPACE/${test} --junit-xml $WORKSPACE/${report_file}
"""
} catch (exc) {
input message: "Non-root access test failed. Click Proceed or Abort when you are done debugging on the instance."
throw exc
} finally {
junit healthScaleFactor: 10.0, testResults: report_file
}
}
}
}
}

if (test_xdma) {
all_tests['Test XDMA Driver'] = {
stage('Test XDMA Driver') {
Expand Down
1 change: 0 additions & 1 deletion README.md
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Expand Up @@ -141,7 +141,6 @@ The [SDK directory](./sdk/README.md) includes the runtime environment required t
* Linux Kernel Drivers - The developer kit includes three drivers:
* [XDMA Driver](sdk/linux_kernel_drivers/xdma/README.md) - DMA interface to/from HDK accelerators.
* [XOCL Driver](sdk/linux_kernel_drivers/xocl) - DMA interface with software defined accelerators (also called hardware kernels).
* [EDMA Driver](sdk/linux_kernel_drivers/edma/README.md) - Legacy DMA interface to/from HDK accelerators.
* [FPGA Libraries](sdk/userspace/fpga_libs) - APIs used by C/C++ host applications.
* [FPGA Management Tools](sdk/userspace/fpga_mgmt_tools/README.md) - AFI management APIs for runtime loading/clearing FPGA image, gathering metrics and debug interface on the F1 instance.

Expand Down
33 changes: 32 additions & 1 deletion RELEASE_NOTES.md
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Expand Up @@ -26,6 +26,37 @@
* 1 DDR controller implemented in the SH (always available)
* 3 DDR controllers implemented in the CL (configurable number of implemented controllers allowed)

## Release 1.4.6 (See [ERRATA](./ERRATA.md) for unsupported features)

* Fixes SDx 2018.2 [missing profile report items in SDAccel](https://forums.aws.amazon.com/thread.jspa?threadID=293541&tstart=0)
* Requires [Xilinx 2018.2 Patch AR71715](hdk/docs/SDxPatch_AR71715_and_XRT_installation_instructions.md#installing-sdx-20182-tool-patch-ar71715)
* Requires [Xilinx runtime release 2018.2_XDF.RC4](https://github.com/Xilinx/XRT/tree/2018.2_XDF.RC4)
* Please see patching & XRT installation instructions [here](hdk/docs/SDxPatch_AR71715_and_XRT_installation_instructions.md)
* Fixes SDx 2018.2 [multithreaded kernel driver scheduling](https://forums.aws.amazon.com/thread.jspa?threadID=293166&tstart=0)
* Requires [Xilinx runtime release 2018.2_XDF.RC4](https://github.com/Xilinx/XRT/tree/2018.2_XDF.RC4)
* Please see XRT installation instructions [here](hdk/docs/SDxPatch_AR71715_and_XRT_installation_instructions.md#installing-xilinx-runtime-xrt-20182_xdfrc4)
* EDMA Driver is no longer supported.
* AWS strongly recommends moving your applications to [XDMA](sdk/linux_kernel_drivers/xdma/README.md).
* [EDMA Driver](sdk/linux_kernel_drivers/edma/README.md) will be fully removed from Developer kit 1.4.7+.
* Fixed Issues
* [NULL definition include in header file](https://github.com/aws/aws-fpga/pull/414)
* [Improved messaging for AFI builder script](https://github.com/aws/aws-fpga/pull/407)
* [Fixes address decoding to DDR slaves in cl_dram_dma example](hdk/cl/examples/cl_dram_dma/design)
* Improvements
* [Improves SDK FPGA managment tools error messaging](sdk/userspace/fpga_mgmt_tools/README.md)
* [Enhanced DMA lib for general device number mapping](sdk/userspace/fpga_libs/fpga_dma/fpga_dma_utils.c)
* [Improved guidelines for AFI power managment](hdk/docs/afi_power.md)
* [Improved Streaming Data Engine IP Integration Documentation](sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.md)

* Package versions used to validate SDAccel runtime

| Package | AMI 1.5.0 [SDx 2018.2] | AMI 1.4.0 [SDx 2017.4] |
|---------|------------------------|------------------------|
| kernel | 3.10.0-862.11.6.el7.x86_64 | 3.10.0-693.21.1.el7.x86_64 |
| kernel-devel | 3.10.0-862.11.6.el7.x86_64 | 3.10.0-693.21.1.el7.x86_64 |
| LIBSTDC++ | libstdc++-4.8.5-36.el7.x86_64 | libstdc++-4.8.5-16.el7_4.2.x86_64 |


## Release 1.4.5 (See [ERRATA](./ERRATA.md) for unsupported features)

* [Documents SDAccel Runtime compatibility](SDAccel/docs/Create_Runtime_AMI.md#runtime-ami-compatability-table)
Expand Down Expand Up @@ -93,7 +124,7 @@ Look for the ./hdk/hdk_version.txt file.

**Q: How do I know what my Shell version is? **

The Shell version of an FPGA slot is available through the FPGA Image Management tools. See the description of `fpga-describe-local-image` for more details on retrieving the shell version from a slot.
The Shell version of an FPGA slot is available through the FPGA Image Management tools after an AFI has been loaded. See the description of `fpga-describe-local-image` for more details on retrieving the shell version from a slot. Prior to loading an AFI, the state of the FPGA (including shell version) is undefined and non-deterministic.

**Q: How do I know what version of FPGA Image management tools are running on my instance? **

Expand Down
13 changes: 3 additions & 10 deletions SDAccel/README.md
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Expand Up @@ -125,6 +125,8 @@ The instructions below describe how to build the Xilinx FPGA Binary and host app
$ make TARGETS=hw DEVICES=$AWS_PLATFORM all
```

NOTE: If you encounter an error with `No current synthesis run set`, you may have previously run the [HDK IPI examples](../hdk/docs/IPI_GUI_Vivado_Setup.md) and created a `Vivado_init.tcl` file in `~/.Xilinx/Vivado`. This will cause [problems](https://forums.aws.amazon.com/thread.jspa?threadID=268202&tstart=25) with the build process, thus it is recommended to remove it before starting a hardware system build.

Now that you have built your Xilinx FPGA binary, see [SDAccel Power Analysis Guide](./docs/SDAccel_Power_Analysis.md) for more details on how to analyze power for your binary.

<a name="createafi"></a>
Expand Down Expand Up @@ -209,20 +211,11 @@ Here are the steps:
* Ensure the host application can find and load the \*.awsxclbin AWS FPGA binary file.

* Source the Runtime Environment & Execute your Host Application
* Xilinx SDx 2017.4:
```
$ sudo sh
# source /opt/Xilinx/SDx/2017.4.rte.dyn/setup.sh # Other runtime env settings needed by the host app should be setup after this step
# ./helloworld
```

* Xilinx SDx 2018.2:
```
$ sudo sh
# source /opt/xilinx/xrt/setup.sh # Other runtime env settings needed by the host app should be setup after this step
# source $AWS_FPGA_REPO_DIR/sdaccel_runtime_setup.sh # Other runtime env settings needed by the host app should be setup after this step
# ./helloworld
```


<a name="read"></a>
# Additional SDAccel Information (2017.4)
Expand Down
38 changes: 28 additions & 10 deletions SDAccel/docs/Create_Runtime_AMI.md
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Expand Up @@ -51,25 +51,43 @@

## 2. Copy required Xilinx SDAccel Runtime Libraries to the Instance and Reboot your Runtime Instance.

* Using an instance running [FPGA Developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) or an on-premises machine with access to a Xilinx SDAccel Tools Installation, run the following:
* Using an instance running [FPGA Developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) or an on-premises machine with access to a Xilinx SDAccel Tools Installation, first source $AWS_FPGA_REPO_DIR/sdaccel_setup.sh and then run following commands:

* if using Ubuntu or debian distribution set GLIBPATH env variable to Ubuntu. If using any other OS distribution set GLIBPATH to default.

* set env variable 'XLNXRTE' to intended runtime install directory path.

### **For Vivado SDX 2017.4**

````
$ mkdir -p xlnxrte/lib/lnx64.o
$ mkdir -p xlnxrte/runtime/bin
$ cp $XIILNX_SDX/lib/lnx64.o/libstdc++.so* xlnxrte/lib/lnx64.o/.
$ cp $XIILNX_SDX/lib/lnx64.o/libxilinxopencl.so xlnxrte/lib/lnx64.o/.
$ cp $XIILNX_SDX/runtime/bin/xclbinsplit xlnxrte/runtime/bin
$ cp $XIILNX_SDX/runtime/bin/xclbincat xlnxrte/runtime/bin
$ export GLIBPATH= <Ubuntu or default -- see note above>
$ export XLNXRTE=<your runtime install directory path>
$ mkdir -p $XLNXRTE/runtime/platforms/$(DSA)/driver
$ mkdir -p $XLNXRTE/lib/lnx64.o
$ mkdir -p $XLNXRTE/runtime/bin
$ mkdir -p $XLNXRTE/runtime/lib/x86_64
$ cp $SDACCEL_DIR/userspace/src2/libxrt-aws.so $XLNXRTE/runtime/platforms/xilinx_aws-vu9p-f1-04261818_dynamic_5_0/driver/
$ cp $SDACCEL_DIR/tools/awssak2/xbsak $XLNXRTE/runtime/bin/
$ cp $XIILNX_SDX/lib/lnx64.o/$GLIBPATH/libstdc++.so* xlnxrte/lib/x86_64/
$ cp $XIILNX_SDX/runtime/bin/xclbinsplit xlnxrte/runtime/bin/
$ cp $XIILNX_SDX/runtime/bin/xclbincat xlnxrte/runtime/bin/
$ cp $SDACCEL_DIR/aws_platform/xilinx_aws-vu9p-f1-04261818_dynamic_5_0/sw/lib/x86_64/libxilinxopencl.so $XLNXRTE/runtime/lib/x86_64/
$ cp /opt/Xilinx/SDx/2017.4.rte.dyn/setup.sh $XLNXRTE/
$ cp /opt/Xilinx/SDx/2017.4.rte.dyn/setup.csh $XLNXRTE/
````
* You may need to update path in $XLNXRTE/setup.sh and $XLNXRTE/setup.csh script to match your runtime instance.
* Copy $XLNXRTE directory created to $HOME on your Runtime Instance.

* Copy xlnxrte directory created to $HOME on your Runtime Instance.

### **For Vivado SDX 2018.2**

please refer to [Installing the Xilinx Runtime](https://www.xilinx.com/html_docs/xilinx2018_2_xdf/sdaccel_doc/ejy1538090924727.html) for instructions on how to install runtime on your AMI.


## 3. Install Runtime Drivers and run your FPGA accelerated application on your Runtime Instance.
* Log back on to the Runtime Instance:

```
$ export XILINX_SDX=$HOME/xlnxrte
$ export XILINX_SDX=$HOME/$XLNXRTE
````
* You should be able to [run your FPGA accelerated application as described here](https://github.com/aws/aws-fpga/tree/master/SDAccel#runonf1), without needing to launch a new F1 instance

Expand Down
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