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The documentation does not seem to describe how the multiple FPGAs are all interconnected in the larger F2 x4 and x8 systems. Do those instances simply contain 8 single-FPGA boards that can only communicate over PCIe through the host, or could one potentially split a larger design over multiple FPGA instances? If yes, what interface capabilities exist for direct FPGA-to-FPGA communication?
I suspect this may be a common question, so some reference in the high-level HDK documentation might be helpful to others as well.
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