Synchronous load clear rescan (#29)

* Changing hdk_version to 1.2.1

* Fixing the programmer view

* spelling and grammer fixes

* enhanced sdk install script for increased portability

Various Linux distributions have different preferred paths for installations of
unmanaged user binaries and libraries. This change attempts to follow those
preferences while maintaining maximum portability.

This script has been tested recent versions (at time of writing) of:
 - Amazon Linux 2017.03
 - Centos (FPGA Dev AMI 1.2)
 - Ubuntu 16.04.2 LTS
 - SUSE 12

It has not been tested on RHEL, but is presumed to work since it is similar
to Amazon Linux and Centos.

It installs binaries to /usr/local/bin if it's on the sudo PATH or /usr/bin
otherwise. It installs the shared library the first directory it finds searching
from the follwing list:
 /usr/local/lib64
 /usr/local/lib
 /usr/lib64
 /usr/lib
This usually results in installations to /usr/local/lib on Ubuntu and to
/usr/local/lib64 on others.

* removed "known bug" for Ubuntu

* fixed an error return code

When the mailbox command timesout, return the -ETIMEDOUT. Negative
values are decoded from errno.h and positive number are defined by the
library.

* set the mbox timeout and delay when using --request-timeout

* updated fpga_pci_bar_attach to close fd after mmap

* Rj doc updates (#23)

* Placed the rescan option in bold text

* Placed the rescan option in bold text and italics

* Renaming Chipscope to Virtual JTAG; Additional clock recipes.

Change-Id: Ie4c8fb77893e011adcf85756c0e5d55e93f1fa9a

* Renaming disable chipscope define in sim .f files.

Change-Id: Ie99a86f1fd8639b614a618c6eb9a38a9e7358e4b

* Synchrnous load and clear operations with auto-rescan and end-state display (#27)

Synchronous load and clear operations with auto-rescan and end-state display

* Updated README.md (#28)

Author: AWSrobertmj

FAQs.md

@@ -204,7 +204,7 @@ We encourage you to use the [AWS FPGA Developer Forum](https://forums.aws.amazon
 
 The required AWS software is the [FPGA Management Tool set](./sdk/userspace/fpga_mgmt_tools). This software manages loading and clearing AFIs for the instance FPGAs. It also allows developers to retrieve FPGAs status from within the instance. Users will need to load the F1 AMI with the drivers and runtime libraries needed for their FPGA application.
 
-Typically, you will not need the HDK nor any Xilinx Vivado tools on an F1 instance that is using prebuilt AFIs; unless, you want to do in-field debug using Vivado's ChipScope.
+Typically, you will not need the HDK nor any Xilinx Vivado tools on an F1 instance that is using prebuilt AFIs; unless, you want to do in-field debug using Vivado's ChipScope (Virtual JTAG).
 
 
 ## Marketplace
@@ -235,7 +235,7 @@ There are two types of interfaces from the instance host CPU to the FPGAs:
 
 The first is the FPGA Image Management Tools. These APIs are detailed in the [SDK portion](./sdk/userspace/fpga_mgmt_tools) of the GitHub repository. FPGA Image Management Tools include APIs to load, clear, and get status of the FPGA. 
 
-The second type of interface is direct address access to the Application PCIe Physical Functions (PF) of the FPGA. There is no API for this access. Rather, there is direct access to resources in the Custom Logic (CL) region or Shell that can be accessed by software written on the instance. For example, the ChipScope software uses address space in a PF to provide FPGA debug support. Developers can create any API to the resources in their CL. See the [Shell Interface Specification](./hdk/docs/AWS_Shell_Interface_Specification.md) for more details on the address space mapping as seen from the instance.
+The second type of interface is direct address access to the Application PCIe Physical Functions (PF) of the FPGA. There is no API for this access. Rather, there is direct access to resources in the Custom Logic (CL) region or Shell that can be accessed by software written on the instance. For example, the ChipScope software (Virtual JTAG) uses address space in a PF to provide FPGA debug support. Developers can create any API to the resources in their CL. See the [Shell Interface Specification](./hdk/docs/AWS_Shell_Interface_Specification.md) for more details on the address space mapping as seen from the instance.
 
 
 
@@ -379,7 +379,7 @@ Yes. The HDK includes a simulation model for the AWS shell. See the [HDK common
 
 **Q: What resources within the FPGA does the AWS Shell consume?**
 
-The Shell consumes about 20% of the FPGA resources, and that includes the PCIe Gen3 X16, DMA engine, DRAM controller interface, ChipScope and other health monitoring and image loading logic. No modifications to the Shell or the partition pins between the Shell and the Custom Logic are possible by the FPGA developer.
+The Shell consumes about 20% of the FPGA resources, and that includes the PCIe Gen3 X16, DMA engine, DRAM controller interface, ChipScope (Virtual JTAG) and other health monitoring and image loading logic. No modifications to the Shell or the partition pins between the Shell and the Custom Logic are possible by the FPGA developer.
 
 
 

RELEASE_NOTES.md

@@ -31,7 +31,7 @@
    *    EDMA Performance improvments 
    *    Expanded EC2 Instance type support
    *    CL Examples @250Mhz (Clock recipe A1)
-   *    Option to exclude chipscope from building CL examples (DISABLE_CHIPSCOPE_DEBUG)
+   *    Option to exclude Chipscope (Virtual JTAG) from building CL examples (DISABLE_VJTAG_DEBUG)
 
 # Release 1.2.0
 

hdk/cl/examples/cl_dram_dma/design/cl_dram_dma.sv

@@ -720,7 +720,7 @@ cl_sda_slv CL_SDA_SLV (
 //-----------------------------------------
 
 
-`ifndef DISABLE_CHIPSCOPE_DEBUG
+`ifndef DISABLE_VJTAG_DEBUG
 
 cl_ila CL_ILA (
 
@@ -751,7 +751,7 @@ cl_vio CL_VIO (
 );
 
 
-`endif //  `ifndef DISABLE_CHIPSCOPE_DEBUG
+`endif //  `ifndef DISABLE_VJTAG_DEBUG
 
 //----------------------------------------- 
 // Virtual JATG ILA Debug core example 

hdk/cl/examples/cl_dram_dma/design/cl_dram_dma_defines.vh

@@ -27,8 +27,8 @@
 //uncomment below to make SH and CL async
 `define SH_CL_ASYNC
 
-// Uncomment to disable Chipscope
-//`define DISABLE_CHIPSCOPE_DEBUG
+// Uncomment to disable Virtual JTAG
+//`define DISABLE_VJTAG_DEBUG
 
 `endif
 

hdk/cl/examples/cl_dram_dma/verif/scripts/top.questa.f

@@ -49,7 +49,7 @@
 ${SH_LIB_DIR}/bram_2rw.sv
 ${SH_LIB_DIR}/flop_fifo.sv
 
-+define+DISABLE_CHIPSCOPE_DEBUG
++define+DISABLE_VJTAG_DEBUG
 ${CL_ROOT}/design/axil_slave.sv
 ${CL_ROOT}/design/cl_dram_dma_defines.vh
 ${CL_ROOT}/design/cl_tst_scrb.sv

hdk/cl/examples/cl_dram_dma/verif/scripts/top.vcs.f

@@ -45,7 +45,7 @@
 ${SH_LIB_DIR}/../ip/axi_register_slice/sim/axi_register_slice.v
 ${SH_LIB_DIR}/../ip/axi_register_slice_light/sim/axi_register_slice_light.v
 
-+define+DISABLE_CHIPSCOPE_DEBUG
++define+DISABLE_VJTAG_DEBUG
 ${CL_ROOT}/design/axil_slave.sv
 ${CL_ROOT}/design/cl_dram_dma_defines.vh
 ${CL_ROOT}/design/cl_tst_scrb.sv

hdk/cl/examples/cl_dram_dma/verif/scripts/top.vivado.f

@@ -47,7 +47,7 @@
 ${SH_LIB_DIR}/../ip/axi_register_slice/sim/axi_register_slice.v
 ${SH_LIB_DIR}/../ip/axi_register_slice_light/sim/axi_register_slice_light.v
 
---define DISABLE_CHIPSCOPE_DEBUG
+--define DISABLE_VJTAG_DEBUG
 ${CL_ROOT}/design/axil_slave.sv
 ${CL_ROOT}/design/cl_dram_dma_defines.vh
 ${CL_ROOT}/design/cl_tst_scrb.sv

hdk/cl/examples/cl_hello_world/design/cl_hello_world.sv

@@ -328,9 +328,9 @@ assign pre_cl_sh_status_vled[15:0] = vled_q[15:0] & sh_cl_status_vdip_q2[15:0];
   assign cl_sh_status1[31:0] = `CL_VERSION;
 
 //-----------------------------------------------
-// Debug bridge, used if need chipscope
+// Debug bridge, used if need Virtual JTAG
 //-----------------------------------------------
-`ifndef DISABLE_CHIPSCOPE_DEBUG
+`ifndef DISABLE_VJTAG_DEBUG
 
 // Flop for timing global clock counter
 logic[63:0] sh_cl_glcount0_q;
@@ -381,7 +381,7 @@ always_ff @(posedge clk_main_a0)
    );
 
 //-----------------------------------------------
-// VIO Example - Needs Chipscope
+// VIO Example - Needs Virtual JTAG
 //-----------------------------------------------
    // Counter running at 125MHz
 
@@ -465,7 +465,7 @@ always_ff @(posedge clk_main_a0)
                    .probe10 (vo_cnt_watermark_q)
                    );
 
-`endif //  `ifndef DISABLE_CHIPSCOPE_DEBUG
+`endif //  `ifndef DISABLE_VJTAG_DEBUG
 
 endmodule
 

hdk/cl/examples/cl_hello_world/design/cl_hello_world_defines.vh

@@ -23,7 +23,7 @@
 // FPGA flop init capability).  This will help with routing resources.
 `define FPGA_LESS_RST
 
-// Uncomment to disable Chipscope
-//`define DISABLE_CHIPSCOPE_DEBUG
+// Uncomment to disable Virtual JTAG
+//`define DISABLE_VJTAG_DEBUG
 
 `endif

hdk/common/shell_v04151701/build/scripts/aws_build_dcp_from_cl.sh

@@ -18,7 +18,7 @@
 # Usage help
 function usage
 {
-    echo "usage: aws_build_dcp_from_cl.sh [ [-script <vivado_script>] | [-strategy BASIC | DEFAULT | EXPLORE | TIMING | CONGESTION] [-clock_recipe_a A0 | A1 | A2] [-clock_recipe_b B0 | B1] [-clock_recipe_c C0 | C1] [-foreground] [-notify] | [-h] | [-H] | [-help] |  ]"
+    echo "usage: aws_build_dcp_from_cl.sh [ [-script <vivado_script>] | [-strategy BASIC | DEFAULT | EXPLORE | TIMING | CONGESTION] [-clock_recipe_a A0 | A1 | A2] [-clock_recipe_b B0 | B1 | B2 | B3 | B4 | B5] [-clock_recipe_c C0 | C1 | C2 | C3] [-foreground] [-notify] | [-h] | [-H] | [-help] |  ]"
     echo " "
     echo "By default the build is run in the background using nohup so that the"
     echo "process will not be terminated if the terminal window is closed."
@@ -123,15 +123,15 @@ fi
 
 # Check that clock_recipe_b is valid
 shopt -s extglob
-if [[ $clock_recipe_b != @(B0|B1) ]]; then
-  err_msg "$clock_recipe_b isn't a valid Clock Group B recipe. Valid Clock Group B recipes are B0 and B1."
+if [[ $clock_recipe_b != @(B0|B1|B2|B3|B4|B5) ]]; then
+  err_msg "$clock_recipe_b isn't a valid Clock Group B recipe. Valid Clock Group B recipes are B0, B1, B2, B3, B4, and B5."
   exit 1
 fi
 
 # Check that clock_recipe_c is valid
 shopt -s extglob
-if [[ $clock_recipe_c != @(C0|C1) ]]; then
-  err_msg "$clock_recipe_c isn't a valid Clock Group C recipe. Valid Clock Group C recipes are C0 and C1."
+if [[ $clock_recipe_c != @(C0|C1|C2|C3) ]]; then
+  err_msg "$clock_recipe_c isn't a valid Clock Group C recipe. Valid Clock Group C recipes are C0, C1, C2, and C3."
   exit 1
 fi