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Merge pull request #26 from aws/AWSCC_new_build
Moved debug_bridge constraints to CL areas
2 parents e182206 + 9b043c0 commit cabdca3

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+98
-11
lines changed

10 files changed

+98
-11
lines changed

‎hdk/cl/examples/cl_dram_dma/build/constraints/cl_debug_bridge.xdc‎

Lines changed: 46 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,46 @@
1+
# Constraints for TCK<->Main Clock
2+
set_clock_groups -name tck_clk_main_a0 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
3+
set_clock_groups -name tck_drck -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck]
4+
set_clock_groups -name tck_userclk -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]
5+
6+
current_instance CL/CL_ILA/CL_DEBUG_BRIDGE/inst/xsdbm/inst/BSCANID_VEC.u_xsdbm_id_vec/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst
7+
8+
set wr_clock [get_clocks -of_objects [get_ports -scoped_to_current_instance clk]]
9+
set rd_clock [get_clocks -of_objects [get_ports -scoped_to_current_instance tck]]
10+
set wr_clk_period [get_property PERIOD $wr_clock]
11+
set rd_clk_period [get_property PERIOD $rd_clock]
12+
set skew_value [expr {(($wr_clk_period < $rd_clk_period) ? $wr_clk_period : $rd_clk_period)} ]
13+
14+
# Ignore paths from the write clock to the read data registers for Asynchronous Distributed RAM based FIFO
15+
set_false_path -from [filter [all_fanout -from [get_ports -scoped_to_current_instance clk] -flat -endpoints_only] {IS_LEAF}] -to [get_cells -hierarchical -filter {NAME =~ *gdm.dm_gen.dm*/gpr1.dout_i_reg*}]
16+
17+
# Set max delay on cross clock domain path for Block/Distributed RAM based FIFO
18+
19+
set_max_delay -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*rd_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].wr_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $rd_clock]
20+
set_bus_skew -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*rd_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].wr_stg_inst/Q_reg_reg[*]] $skew_value
21+
22+
set_max_delay -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*wr_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].rd_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $wr_clock]
23+
set_bus_skew -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*wr_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].rd_stg_inst/Q_reg_reg[*]] $skew_value
24+
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current_instance
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current_instance CL/CL_ILA/CL_DEBUG_BRIDGE/inst/xsdbm/inst/BSCANID_VEC.u_xsdbm_id_vec/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst
28+
29+
set wr_clock [get_clocks -of_objects [get_ports -scoped_to_current_instance tck]]
30+
set rd_clock [get_clocks -of_objects [get_ports -scoped_to_current_instance clk]]
31+
set wr_clk_period [get_property PERIOD $wr_clock]
32+
set rd_clk_period [get_property PERIOD $rd_clock]
33+
set skew_value [expr {(($wr_clk_period < $rd_clk_period) ? $wr_clk_period : $rd_clk_period)} ]
34+
35+
# Ignore paths from the write clock to the read data registers for Asynchronous Distributed RAM based FIFO
36+
set_false_path -from [filter [all_fanout -from [get_ports -scoped_to_current_instance tck] -flat -endpoints_only] {IS_LEAF}] -to [get_cells -hierarchical -filter {NAME =~ *gdm.dm_gen.dm*/gpr1.dout_i_reg*}]
37+
38+
# Set max delay on cross clock domain path for Block/Distributed RAM based FIFO
39+
40+
set_max_delay -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*rd_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].wr_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $rd_clock]
41+
set_bus_skew -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*rd_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].wr_stg_inst/Q_reg_reg[*]] $skew_value
42+
43+
set_max_delay -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*wr_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].rd_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $wr_clock]
44+
set_bus_skew -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*wr_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/*gsync_stage[1].rd_stg_inst/Q_reg_reg[*]] $skew_value
45+
46+
current_instance

‎hdk/cl/examples/cl_dram_dma/build/scripts/apply_debug_constraints.tcl‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
#checking if HDK_SHELL_DIR env variable exists
2+
if { [info exists ::env(HDK_SHELL_DIR)] } {
3+
set HDK_SHELL_DIR $::env(HDK_SHELL_DIR)
4+
puts "Using Shell directory $HDK_SHELL_DIR";
5+
} else {
6+
puts "Error: HDK_SHELL_DIR environment variable not defined ! ";
7+
puts "Run the hdk_setup.sh script from the root directory of aws-fpga";
8+
exit 2
9+
}
10+
11+
#checking if CL_DIR env variable exists
12+
if { [info exists ::env(CL_DIR)] } {
13+
set CL_DIR $::env(CL_DIR)
14+
puts "Using CL directory $CL_DIR";
15+
} else {
16+
puts "Error: CL_DIR environment variable not defined ! ";
17+
puts "Run the hdk_setup.sh script from the root directory of aws-fpga";
18+
exit 2
19+
}
20+
21+
if {[llength [get_cells -quiet CL/CL_ILA/CL_DEBUG_BRIDGE]]} {
22+
puts "AWS FPGA: Found debug_bridge instance in CL. Processing debug constraints"
23+
read_xdc $CL_DIR/build/constraints/cl_debug_bridge.xdc
24+
read_xdc -cell CL/CL_ILA/CL_DEBUG_BRIDGE/inst/xsdbm/inst $HDK_SHELL_DIR/build/constraints/xsdbm_timing_exception.xdc
25+
}

‎hdk/cl/examples/cl_dram_dma/build/scripts/create_dcp_from_cl.tcl‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -211,7 +211,8 @@ if {$implement} {
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212212
#Read the constraints, note *DO NOT* read cl_clocks_aws (clocks originating from AWS shell)
213213
read_xdc [ list \
214-
$CL_DIR/build/constraints/cl_pnr_user.xdc \
214+
$HDK_SHELL_DIR/build/constraints/cl_pnr_aws.xdc \
215+
$CL_DIR/build/constraints/cl_pnr_user.xdc
215216
]
216217
set_property PROCESSING_ORDER late [get_files cl_pnr_user.xdc]
217218

@@ -243,9 +244,9 @@ if {$implement} {
243244
}
244245

245246
# Constraints for TCK<->Main Clock
246-
set_clock_groups -name tck_clk_main_a0 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
247-
set_clock_groups -name tck_drck -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck]
248-
set_clock_groups -name tck_userclk -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]
247+
#set_clock_groups -name tck_clk_main_a0 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
248+
#set_clock_groups -name tck_drck -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck]
249+
#set_clock_groups -name tck_userclk -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]
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########################

‎hdk/common/shell_v04151701/build/constraints/cl_debug_bridge.xdc‎ renamed to ‎hdk/cl/examples/cl_hello_world/build/constraints/cl_debug_bridge.xdc‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,8 @@
1+
# Constraints for TCK<->Main Clock
2+
set_clock_groups -name tck_clk_main_a0 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
3+
set_clock_groups -name tck_drck -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck]
4+
set_clock_groups -name tck_userclk -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]
5+
16
current_instance CL/CL_DEBUG_BRIDGE/inst/xsdbm/inst/BSCANID_VEC.u_xsdbm_id_vec/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst
27

38
set wr_clock [get_clocks -of_objects [get_ports -scoped_to_current_instance clk]]

‎hdk/common/shell_v04151701/build/scripts/apply_debug_constraints.tcl‎ renamed to ‎hdk/cl/examples/cl_hello_world/build/scripts/apply_debug_constraints.tcl‎

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,18 @@ if { [info exists ::env(HDK_SHELL_DIR)] } {
88
exit 2
99
}
1010

11-
if {[llength [get_cells -quiet CL/CL_DEBUG_BRIDGE]]} {
11+
#checking if CL_DIR env variable exists
12+
if { [info exists ::env(CL_DIR)] } {
13+
set CL_DIR $::env(CL_DIR)
14+
puts "Using CL directory $CL_DIR";
15+
} else {
16+
puts "Error: CL_DIR environment variable not defined ! ";
17+
puts "Run the hdk_setup.sh script from the root directory of aws-fpga";
18+
exit 2
19+
}
20+
21+
if {[llength [get_cells -quiet CL/CL_DEBUG_BRIDGE]] } {
1222
puts "AWS FPGA: Found debug_bridge instance in CL. Processing debug constraints"
13-
read_xdc $HDK_SHELL_DIR/build/constraints/cl_debug_bridge.xdc
23+
read_xdc $CL_DIR/build/constraints/cl_debug_bridge.xdc
1424
read_xdc -cell CL/CL_DEBUG_BRIDGE/inst/xsdbm/inst $HDK_SHELL_DIR/build/constraints/xsdbm_timing_exception.xdc
1525
}

‎hdk/common/shell_v04151701/build/scripts/strategy_BASIC.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ set opt_preHookTcl ""
2121
set place 1
2222
set place_options ""
2323
set place_directive ""
24-
set place_preHookTcl "$HDK_SHELL_DIR/build/scripts/prohibit_tr.tcl $HDK_SHELL_DIR/build/scripts/apply_debug_constraints.tcl $HDK_SHELL_DIR/build/scripts/cl_xpr_xdc.tcl"
24+
set place_preHookTcl "$HDK_SHELL_DIR/build/scripts/prohibit_tr.tcl $CL_DIR/build/scripts/apply_debug_constraints.tcl $HDK_SHELL_DIR/build/scripts/cl_xpr_xdc.tcl"
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2626
set phys_opt 0
2727
set phys_options ""

‎hdk/common/shell_v04151701/build/scripts/strategy_CONGESTION.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ set opt_preHookTcl ""
2121
set place 1
2222
set place_options ""
2323
set place_directive "AltSpreadLogic_medium"
24-
set place_preHookTcl "$HDK_SHELL_DIR/build/scripts/prohibit_tr.tcl $HDK_SHELL_DIR/build/scripts/apply_debug_constraints.tcl $HDK_SHELL_DIR/build/scripts/cl_xpr_xdc.tcl"
24+
set place_preHookTcl "$HDK_SHELL_DIR/build/scripts/prohibit_tr.tcl $CL_DIR/build/scripts/apply_debug_constraints.tcl $HDK_SHELL_DIR/build/scripts/cl_xpr_xdc.tcl"
2525

2626
set phys_opt 1
2727
set phys_options ""

‎hdk/common/shell_v04151701/build/scripts/strategy_DEFAULT.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ set opt_preHookTcl ""
2121
set place 1
2222
set place_options ""
2323
set place_directive "Explore"
24-
set place_preHookTcl "$HDK_SHELL_DIR/build/scripts/prohibit_tr.tcl $HDK_SHELL_DIR/build/scripts/apply_debug_constraints.tcl $HDK_SHELL_DIR/build/scripts/cl_xpr_xdc.tcl"
24+
set place_preHookTcl "$HDK_SHELL_DIR/build/scripts/prohibit_tr.tcl $CL_DIR/build/scripts/apply_debug_constraints.tcl $HDK_SHELL_DIR/build/scripts/cl_xpr_xdc.tcl"
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2626
set phys_opt 1
2727
set phys_options ""

‎hdk/common/shell_v04151701/build/scripts/strategy_EXPLORE.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ set opt_preHookTcl ""
2121
set place 1
2222
set place_options ""
2323
set place_directive "Explore"
24-
set place_preHookTcl "$HDK_SHELL_DIR/build/scripts/prohibit_tr.tcl $HDK_SHELL_DIR/build/scripts/apply_debug_constraints.tcl $HDK_SHELL_DIR/build/scripts/cl_xpr_xdc.tcl"
24+
set place_preHookTcl "$HDK_SHELL_DIR/build/scripts/prohibit_tr.tcl $CL_DIR/build/scripts/apply_debug_constraints.tcl $HDK_SHELL_DIR/build/scripts/cl_xpr_xdc.tcl"
2525

2626
set phys_opt 1
2727
set phys_options ""

‎hdk/common/shell_v04151701/build/scripts/strategy_TIMING.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ set opt_preHookTcl ""
2121
set place 1
2222
set place_options ""
2323
set place_directive "ExtraNetDelay_high"
24-
set place_preHookTcl "$HDK_SHELL_DIR/build/scripts/prohibit_tr.tcl $HDK_SHELL_DIR/build/scripts/apply_debug_constraints.tcl $HDK_SHELL_DIR/build/scripts/cl_xpr_xdc.tcl"
24+
set place_preHookTcl "$HDK_SHELL_DIR/build/scripts/prohibit_tr.tcl $CL_DIR/build/scripts/apply_debug_constraints.tcl $HDK_SHELL_DIR/build/scripts/cl_xpr_xdc.tcl"
2525

2626
set phys_opt 1
2727
set phys_options ""

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