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kristopkkristopk
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Merge pull request #81 from aws/woods_update_2
Woods update 2
2 parents 0bc7a23 + 5db33dc commit 3a0a510

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16 files changed

+123
-183
lines changed

16 files changed

+123
-183
lines changed

‎hdk/cl/examples/cl_dram_dma/build/constraints/cl_debug_bridge.xdc‎

Lines changed: 0 additions & 46 deletions
This file was deleted.

‎hdk/cl/examples/cl_dram_dma/build/scripts/create_dcp_from_cl.tcl‎

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -206,7 +206,6 @@ if {$implement} {
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#Read the constraints, note *DO NOT* read cl_clocks_aws (clocks originating from AWS shell)
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read_xdc [ list \
209-
$HDK_SHELL_DIR/build/constraints/cl_pnr_aws.xdc \
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$CL_DIR/build/constraints/cl_pnr_user.xdc
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]
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set_property PROCESSING_ORDER late [get_files cl_pnr_user.xdc]
@@ -239,12 +238,6 @@ if {$implement} {
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}
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}
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242-
# Constraints for TCK<->Main Clock
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#set_clock_groups -name tck_clk_main_a0 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
244-
#set_clock_groups -name tck_drck -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck]
245-
#set_clock_groups -name tck_userclk -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]
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########################
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# CL Place
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########################

‎hdk/cl/examples/cl_dram_dma/build/scripts/synth_cl_dram_dma.tcl‎

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Original file line numberDiff line numberDiff line change
@@ -85,6 +85,7 @@ puts "AWS FPGA: Reading AWS constraints";
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read_xdc [ list \
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$CL_DIR/build/constraints/cl_clocks_aws.xdc \
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$HDK_SHELL_DIR/build/constraints/cl_ddr.xdc \
88+
$HDK_SHELL_DIR/build/constraints/cl_synth_aws.xdc \
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$CL_DIR/build/constraints/cl_synth_user.xdc
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]
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‎hdk/cl/examples/cl_hello_world/build/constraints/cl_debug_bridge.xdc‎

Lines changed: 0 additions & 46 deletions
This file was deleted.

‎hdk/cl/examples/cl_hello_world/build/scripts/create_dcp_from_cl.tcl‎

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -206,7 +206,6 @@ if {$implement} {
206206

207207
#Read the constraints, note *DO NOT* read cl_clocks_aws (clocks originating from AWS shell)
208208
read_xdc [ list \
209-
$HDK_SHELL_DIR/build/constraints/cl_pnr_aws.xdc \
210209
$CL_DIR/build/constraints/cl_pnr_user.xdc
211210
]
212211
set_property PROCESSING_ORDER late [get_files cl_pnr_user.xdc]
@@ -239,12 +238,6 @@ if {$implement} {
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}
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}
241240

242-
# Constraints for TCK<->Main Clock
243-
#set_clock_groups -name tck_clk_main_a0 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
244-
#set_clock_groups -name tck_drck -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck]
245-
#set_clock_groups -name tck_userclk -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]
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########################
249242
# CL Place
250243
########################

‎hdk/cl/examples/cl_hello_world/build/scripts/synth_cl_hello_world.tcl‎

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Original file line numberDiff line numberDiff line change
@@ -76,6 +76,7 @@ puts "AWS FPGA: Reading AWS constraints";
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read_xdc [ list \
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$CL_DIR/build/constraints/cl_clocks_aws.xdc \
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$HDK_SHELL_DIR/build/constraints/cl_ddr.xdc \
79+
$HDK_SHELL_DIR/build/constraints/cl_synth_aws.xdc \
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$CL_DIR/build/constraints/cl_synth_user.xdc
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]
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‎hdk/cl/examples/cl_hello_world_vhdl/build/constraints/cl_debug_bridge.xdc‎

Lines changed: 0 additions & 46 deletions
This file was deleted.

‎hdk/cl/examples/cl_hello_world_vhdl/build/scripts/create_dcp_from_cl.tcl‎

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -206,7 +206,6 @@ if {$implement} {
206206

207207
#Read the constraints, note *DO NOT* read cl_clocks_aws (clocks originating from AWS shell)
208208
read_xdc [ list \
209-
$HDK_SHELL_DIR/build/constraints/cl_pnr_aws.xdc \
210209
$CL_DIR/build/constraints/cl_pnr_user.xdc
211210
]
212211
set_property PROCESSING_ORDER late [get_files cl_pnr_user.xdc]
@@ -239,12 +238,6 @@ if {$implement} {
239238
}
240239
}
241240

242-
# Constraints for TCK<->Main Clock
243-
#set_clock_groups -name tck_clk_main_a0 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
244-
#set_clock_groups -name tck_drck -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck]
245-
#set_clock_groups -name tck_userclk -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]
246-
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248241
########################
249242
# CL Place
250243
########################

‎hdk/cl/examples/cl_hello_world_vhdl/build/scripts/synth_cl_hello_world.tcl‎

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Original file line numberDiff line numberDiff line change
@@ -83,6 +83,7 @@ puts "AWS FPGA: Reading AWS constraints";
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# cl_synth_user.xdc - Developer synthesis constraints.
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read_xdc [ list \
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$CL_DIR/build/constraints/cl_clocks_aws.xdc \
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$HDK_SHELL_DIR/build/constraints/cl_synth_aws.xdc \
8687
$HDK_SHELL_DIR/build/constraints/cl_ddr.xdc \
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$CL_DIR/build/constraints/cl_synth_user.xdc
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]

‎hdk/common/shell_v062517b4/build/constraints/cl_clocks_aws.xdc‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
#---------------------------------------
2+
# Create Clock Constraints - CL
3+
#---------------------------------------
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create_clock -period 4.000 -name cl_clk0 -waveform {0.000 2.000} [get_ports clk_main_a0]
5+
set_false_path -from [get_ports rst_main_n]

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