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lines changed- hdk
- cl/examples/cl_dram_dma/design
- common
- shell_v032117d7
- build
- constraints
- scripts
- design
- interfaces
- ip
- axi_clock_converter_0
- doc
- hdl
- simulation
- sim
- synth
- axi_register_slice_light
- doc
- hdl
- sim
- synth
- axi_register_slice
- doc
- hdl
- sim
- synth
- cl_axi_interconnect
- hdl
- hw_handoff
- ip
- cl_axi_interconnect_axi_interconnect_0_0
- cl_axi_interconnect_m00_regslice_0
- sim
- synth
- cl_axi_interconnect_m01_regslice_0
- sim
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- cl_axi_interconnect_m02_regslice_0
- sim
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- cl_axi_interconnect_m03_regslice_0
- sim
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- cl_axi_interconnect_s00_regslice_0
- sim
- synth
- cl_axi_interconnect_xbar_0
- sim
- synth
- cl_debug_bridge
- .Xil/Vivado-60721-ip-10-206-21-243/coregen/clock_temp
- bd_0
- hdl
- hw_handoff
- ip
- ip_0
- constraints
- hdl
- verilog
- sim
- synth
- ip_1
- hdl
- sim
- synth
- doc
- sim
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- ddr4_core
- bd_0
- hdl
- hw_handoff
- ip
- ip_0
- data
- hdl
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- synth
- ip_10
- hdl
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- ip_1
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- hdl
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- hdl
- simulation
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- ip_7
- hdl
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- ip_8
- hdl
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- ip_9
- hdl
- simulation
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- synth
- doc
- ip_0
- .Xil/Vivado-113743-ip-10-206-21-184/coregen
- bram_temp
- clock_temp
- reset_temp
- sim
- synth
- ip_1
- par
- rtl
- clocking
- iob
- ip_top
- map
- phy
- xiphy_files
- par
- rtl
- axi_ctrl
- axi
- cal
- clocking
- controller
- ip_top
- ui
- sw/calibration_0/Debug
- tb
- dest_register_slice
- doc
- hdl
- sim
- synth
- ila_0
- doc
- hdl
- verilog
- ila_v6_2/constraints
- sim
- synth
- ila_1
- doc
- hdl
- verilog
- ila_v6_2/constraints
- sim
- synth
- ila_vio_counter
- doc
- hdl
- verilog
- ila_v6_2/constraints
- sim
- synth
- src_register_slice
- doc
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- sim
- synth
- vio_0
- doc
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- verilog
- sim
- synth
- lib
- new_cl_template
- build
- constraints
- scripts
- design
- shell_v04151701
- build
- constraints
- scripts
- design
- interfaces
- ip
- axi_clock_converter_0
- doc
- hdl
- simulation
- sim
- synth
- axi_register_slice_light
- doc
- hdl
- sim
- synth
- axi_register_slice
- doc
- hdl
- sim
- synth
- cl_axi_interconnect_m00_regslice_0
- sim
- synth
- cl_axi_interconnect
- hdl
- hw_handoff
- ip
- cl_axi_interconnect_axi_interconnect_0_0
- cl_axi_interconnect_m00_regslice_0
- sim
- synth
- cl_axi_interconnect_m01_regslice_0
- sim
- synth
- cl_axi_interconnect_m02_regslice_0
- sim
- synth
- cl_axi_interconnect_m03_regslice_0
- sim
- synth
- cl_axi_interconnect_s00_regslice_0
- sim
- synth
- cl_axi_interconnect_s01_regslice_0
- sim
- synth
- cl_axi_interconnect_xbar_0
- sim
- synth
- ui
- cl_debug_bridge
- .Xil/Vivado-60721-ip-10-206-21-243/coregen/clock_temp
- bd_0
- hdl
- hw_handoff
- ip
- ip_0
- constraints
- hdl
- verilog
- sim
- synth
- ip_1
- hdl
- sim
- synth
- doc
- sim
- synth
- ddr4_core
- bd_0
- hdl
- hw_handoff
- ip
- ip_0
- data
- hdl
- sim
- synth
- ip_10
- hdl
- sim
- synth
- ip_1
- hdl
- sim
- synth
- ip_2
- hdl
- sim
- synth
- ip_3
- hdl
- sim
- synth
- ip_4
- hdl
- sim
- synth
- ip_5
- hdl
- sim
- synth
- ip_6
- hdl
- simulation
- sim
- synth
- ip_7
- hdl
- sim
- synth
- ip_8
- hdl
- sim
- synth
- ip_9
- hdl
- simulation
- sim
- synth
- doc
- ip_0
- sim
- synth
- ip_1
- par
- rtl
- clocking
- iob
- ip_top
- map
- phy
- xiphy_files
- par
- rtl
- axi_ctrl
- axi
- cal
- clocking
- controller
- ip_top
- ui
- sw/calibration_0/Debug
- tb
- dest_register_slice
- doc
- hdl
- sim
- synth
- ila_0
- doc
- hdl
- verilog
- ila_v6_2/constraints
- sim
- synth
- ila_1
- doc
- hdl
- verilog
- ila_v6_2/constraints
- sim
- synth
- ila_vio_counter
- doc
- hdl
- verilog
- ila_v6_2/constraints
- sim
- synth
- src_register_slice
- doc
- hdl
- sim
- synth
- vio_0
- doc
- hdl
- verilog
- sim
- synth
- lib
- sh_ddr
- sim
- synth
- new_cl_template
- build
- constraints
- scripts
- design
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