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[SOL] Implement hints of stack stores and loads #163

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Jul 18, 2025
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[SOL] Implement hints of stack stores and loads #163

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70 changes: 70 additions & 0 deletions llvm/lib/Target/SBF/SBFInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -114,6 +114,41 @@ void SBFInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
llvm_unreachable("Can't store this register to stack slot");
}

Register SBFInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex,
unsigned &MemBytes) const {
switch (MI.getOpcode()) {
default:
break;
case SBF::STD_V2:
case SBF::STD_V1:
MemBytes = 8;
if (MI.getOperand(0).isReg() && MI.getOperand(1).isFI() &&
MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
FrameIndex = MI.getOperand(1).getIndex();
return MI.getOperand(0).getReg();
}
break;
case SBF::STW32_V2:
case SBF::STW32_V1:
MemBytes = 4;
if (MI.getOperand(0).isReg() && MI.getOperand(1).isFI() &&
MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
FrameIndex = MI.getOperand(1).getIndex();
return MI.getOperand(0).getReg();
}
break;
}

return 0;
}

Register SBFInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
unsigned MemBytes = 0;
return isStoreToStackSlot(MI, FrameIndex, MemBytes);
}

void SBFInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
Register DestReg, int FI,
Expand All @@ -136,6 +171,41 @@ void SBFInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
llvm_unreachable("Can't load this register from stack slot");
}

Register SBFInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex,
unsigned &MemBytes) const {
switch (MI.getOpcode()) {
default:
break;
case SBF::LDD_V2:
case SBF::LDD_V1:
MemBytes = 8;
if (MI.getOperand(0).isReg() && MI.getOperand(1).isFI() &&
MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
FrameIndex = MI.getOperand(1).getIndex();
return MI.getOperand(0).getReg();
}
break;
case SBF::LDW32_V2:
case SBF::LDW32_V1:
MemBytes = 4;
if (MI.getOperand(0).isReg() && MI.getOperand(1).isFI() &&
MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
FrameIndex = MI.getOperand(1).getIndex();
return MI.getOperand(0).getReg();
}
break;
}

return 0;
}

Register SBFInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
unsigned MemBytes = 0;
return isLoadFromStackSlot(MI, FrameIndex, MemBytes);
}

bool SBFInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
Expand Down
12 changes: 12 additions & 0 deletions llvm/lib/Target/SBF/SBFInstrInfo.h
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Expand Up @@ -68,6 +68,18 @@ class SBFInstrInfo : public SBFGenInstrInfo {
std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
Register Reg) const override;

Register isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;

Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex,
unsigned &MemBytes) const override;

Register isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;

Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex,
unsigned &MemBytes) const override;

private:
bool HasExplicitSignExt;
bool NewMemEncoding;
Expand Down
123 changes: 123 additions & 0 deletions llvm/unittests/Target/SBF/SBFInstrInfoTest.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -125,6 +125,129 @@ TEST_P(SBFInstrInfoTest, IsAddImmediate) {
ASSERT_FALSE(MI7Res.has_value());
}

TEST_P(SBFInstrInfoTest, IsStoreToStackSlot) {
const SBFInstrInfo *TII = ST->getInstrInfo();
DebugLoc DL;

MachineInstr *MI = BuildMI(*MF, DL, TII->get(SBF::STD_V2))
.addReg(SBF::R1, getKillRegState(true))
.addFrameIndex(10)
.addImm(0)
.getInstr();
int FI = 0;
unsigned Mem = 0;
auto MI1Res = TII->isStoreToStackSlot(*MI, FI, Mem);
EXPECT_EQ(MI1Res.id(), SBF::R1);
EXPECT_EQ(FI, 10);
EXPECT_EQ(Mem, 8u);

MI = BuildMI(*MF, DL, TII->get(SBF::STD_V1))
.addReg(SBF::R2, getKillRegState(true))
.addFrameIndex(17)
.addImm(0)
.getInstr();
FI = 0;
Mem = 0;
MI1Res = TII->isStoreToStackSlot(*MI, FI, Mem);
EXPECT_EQ(MI1Res.id(), SBF::R2);
EXPECT_EQ(FI, 17);
EXPECT_EQ(Mem, 8u);

MI = BuildMI(*MF, DL, TII->get(SBF::STW32_V2))
.addReg(SBF::R2, getKillRegState(true))
.addFrameIndex(15)
.addImm(0)
.getInstr();
FI = 0;
Mem = 0;
MI1Res = TII->isStoreToStackSlot(*MI, FI, Mem);
EXPECT_EQ(MI1Res.id(), SBF::R2);
EXPECT_EQ(FI, 15);
EXPECT_EQ(Mem, 4u);

MI = BuildMI(*MF, DL, TII->get(SBF::STW32_V1))
.addReg(SBF::R5, getKillRegState(true))
.addFrameIndex(18)
.addImm(0)
.getInstr();
FI = 0;
Mem = 0;
MI1Res = TII->isStoreToStackSlot(*MI, FI, Mem);
EXPECT_EQ(MI1Res.id(), SBF::R5);
EXPECT_EQ(FI, 18);
EXPECT_EQ(Mem, 4u);

MI = BuildMI(*MF, DL, TII->get(SBF::LDW32_V1), SBF::R1)
.addReg(SBF::R5, getKillRegState(true))
.addFrameIndex(18)
.addImm(0)
.getInstr();
FI = 0;
Mem = 0;
MI1Res = TII->isStoreToStackSlot(*MI, FI, Mem);
EXPECT_EQ(MI1Res.id(), 0u);
}

TEST_P(SBFInstrInfoTest, IsLoadFromStackSlot) {
const SBFInstrInfo *TII = ST->getInstrInfo();
DebugLoc DL;

MachineInstr *MI = BuildMI(*MF, DL, TII->get(SBF::LDD_V2), SBF::R1)
.addFrameIndex(10)
.addImm(0)
.getInstr();
int FI = 0;
unsigned Mem = 0;
auto MI1Res = TII->isLoadFromStackSlot(*MI, FI, Mem);
EXPECT_EQ(MI1Res.id(), SBF::R1);
EXPECT_EQ(FI, 10);
EXPECT_EQ(Mem, 8u);

MI = BuildMI(*MF, DL, TII->get(SBF::LDD_V1), SBF::R2)
.addFrameIndex(17)
.addImm(0)
.getInstr();
FI = 0;
Mem = 0;
MI1Res = TII->isLoadFromStackSlot(*MI, FI, Mem);
EXPECT_EQ(MI1Res.id(), SBF::R2);
EXPECT_EQ(FI, 17);
EXPECT_EQ(Mem, 8u);

MI = BuildMI(*MF, DL, TII->get(SBF::LDW32_V2), SBF::R2)
.addFrameIndex(15)
.addImm(0)
.getInstr();
FI = 0;
Mem = 0;
MI1Res = TII->isLoadFromStackSlot(*MI, FI, Mem);
EXPECT_EQ(MI1Res.id(), SBF::R2);
EXPECT_EQ(FI, 15);
EXPECT_EQ(Mem, 4u);

MI = BuildMI(*MF, DL, TII->get(SBF::LDW32_V1))
.addReg(SBF::R5, getKillRegState(true))
.addFrameIndex(18)
.addImm(0)
.getInstr();
FI = 0;
Mem = 0;
MI1Res = TII->isLoadFromStackSlot(*MI, FI, Mem);
EXPECT_EQ(MI1Res.id(), SBF::R5);
EXPECT_EQ(FI, 18);
EXPECT_EQ(Mem, 4u);

MI = BuildMI(*MF, DL, TII->get(SBF::STD_V2))
.addReg(SBF::R5, getKillRegState(true))
.addFrameIndex(18)
.addImm(0)
.getInstr();
FI = 0;
Mem = 0;
MI1Res = TII->isLoadFromStackSlot(*MI, FI, Mem);
EXPECT_EQ(MI1Res.id(), 0u);
}

} // namespace

INSTANTIATE_TEST_SUITE_P(SBFTest, SBFInstrInfoTest, testing::Values("sbf"));
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