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Projects of the digital logic design lab (Fall01) at the University of Tehran.

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Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
Exp1 - Clock and Periodic Signal Generation		Exp1 - Clock and Periodic Signal Generation
Exp2 - Sequential Synthesis and FPGA Device		Exp2 - Sequential Synthesis and FPGA Device
Exp3 - Function Generator		Exp3 - Function Generator
Exp4 - Accelerator and Wrappers		Exp4 - Accelerator and Wrappers
.gitignore		.gitignore
LICENSE		LICENSE
README.md		README.md

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DLD-Lab-Projects