Socfpga 6.12.33 lts #28
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Load/Probe function of intel_fcs driver creates a svc thread which hog's one of the core continuously Signed-off-by: Chirag Kochar <[email protected]>
…haven LCD driver. The 2 old drivers are not compatible with new kernel API definition and are in obsoleted and non-maintained status, they also lead to building failure issue for our new kernel. Disabled them until we got new requirements for those features. Signed-off-by: Austin Zhang <[email protected]>
… issue Fix unable to detect sdcard issue during bootup by forcing PHY programming for all the sdcard speed. Signed-off-by: Kah Jing Lee <[email protected]>
Add USB, TSN, OCRAM and IO96B ECC node to device tree. Signed-off-by: Niravkumar L Rabara <[email protected]>
Add support for QSPI ECC that is connected to Secure Device Manager(SDM). Since the QSPI ECC is always in secure mode, register access is thru ATF using ARM Secure Monitor Call(SMC). Add Single Event Upset(SEU) support for FPGA Configuration RAM. Signed-off-by: Niravkumar L Rabara <[email protected]>
…stration Set ecc_intmask_set register bit 16&17 to avoid any pending irq before registration in driver probe. Removed invalid register write to system manager. Signed-off-by: Niravkumar L Rabara <[email protected]>
This patch is to to set the clk-csr divider value. The value is set based on the clk_csr_i clock speed and currently the hardware is connected with the l4_sp_clk (100MHz) thus the clk-csr divider need to choose the divider with the value 62, due to that, the csr-clk value need to choose divider option 0. Signed-off-by: Boon Khai Ng <[email protected]>
…layer binding Add a device tree binding for the Intel Agilex5 service layer driver Signed-off-by: Adrian Ng Ho Yin <[email protected]> Signed-off-by: Mahesh Rao <[email protected]>
… style Fix checkpatch warnings in stratix10-svc.c. Signed-off-by: Adrian Ng Ho Yin <[email protected]> Signed-off-by: Mahesh Rao <[email protected]>
…mailbox send command For generic mailbox send command ,we need physical address to be passed to ARM trusted firmware. Signed-off-by: Mahesh Rao <[email protected]>
… SMMU enablement Add altr,smmu_enable_quirk to show SMMU enablement on platform. Signed-off-by: Mahesh Rao <[email protected]>
…irk in Intel Agilex5 Enable altr,smmu_enable_quirk in Intel Agilex5 platform. Signed-off-by: Mahesh Rao <[email protected]>
…rata 88e1510 PHY has an errata that causes the phy downshift counter not cleared on a link powering down/up. This can cause the gigabit link to downshift to a lower speed(100Mbps) intermittently. Disabling and reenabling the downshift feature will clear the downshift counter and this helps PHY to retry the gigabit link upto programmed retry count times before downshifting. Currently observed only for the copper link. Signed-off-by: Rohan G Thomas <[email protected]>
This patch is to update PHY mode with internal delay for the family device socfpga_agilex5_socdk_nand. Signed-off-by: Boon Khai Ng <[email protected]>
Enable I3C node in dts. Signed-off-by: Kah Jing Lee <[email protected]>
Include device tree for Debug daughter card. Signed-off-by: Niravkumar L Rabara <[email protected]>
Create new separate dts for eMMC. Signed-off-by: Kah Jing Lee <[email protected]>
The Altera Triple Speed Ethernet has a SGMII/1000BaseC PCS that can be integrated in several ways. It can either be part of the TSE MAC's address space, accessed through 32 bits accesses on the mapped mdio device 0, or through a dedicated 16 bits register set. This driver allows using the TSE PCS outside of altera TSE's driver, since it can be used standalone by other MACs. Signed-off-by: Tham, Mun Yew <[email protected]>
…ress to 0. This patch is to make the phy address generic so all type of daughter card is supported. Signed-off-by: Boon Khai Ng <[email protected]>
Fix the cacheinfo warning for unable to detect cache hierarchy. Signed-off-by: Kah Jing Lee <[email protected]>
… filter Fix the I3C device with spike filter unable to detect issue by setting tHIGH_INIT to 200ns for first broadcast address. This is according to MIPI SPEC 1.1.1 for first broadcast address. Signed-off-by: Kah Jing Lee <[email protected]>
Fixed DMA handshake ID for SPI tx and rx channels. Moved m25p128 flash node to swvp device tree since its only for SIMICS. Signed-off-by: Niravkumar L Rabara <[email protected]>
… fgpa_mgr node Add altr,smmu_enable_quirk to fpga_mgr node for smmu enabled fpga configuration. Signed-off-by: Adrian Ng Ho Yin <[email protected]>
…d quirk Add checking during stratix10-svc probe for smmu enabled quirk. Signed-off-by: Adrian Ng Ho Yin <[email protected]>
Update IOVA carveout limit address by decrementing IOMMU_LIMIT_ADDR by 1 page size to make sure IOVA allocated is within addressable range by SDM. Signed-off-by: Adrian Ng Ho Yin <[email protected]>
…ointer to fpga_mgr Fix fpga_mgr_register not returning pointer to fpga_mgr causing kernel panic during stratix10-soc driver unload. Signed-off-by: Adrian Ng Ho Yin <[email protected]>
…tratix10-soc buffers Refactor memory allocation for fpga reconfiguration buffer to be done during driver probe and memory free to be done during driver remove to fix CMD SYNC timeout in smmu during memory free. Memory allocated will be persistent thoughout the lifetime of the driver. Refactor fpga configuration completion termination condition. Add checking for smmu enabled quirk. Signed-off-by: Adrian Ng Ho Yin <[email protected]>
… agilex5 compatible string Update fpga-mgr bindings with agilex 5 compatible string. Add smmu enable quirk as optional properties. Signed-off-by: Adrian Ng Ho Yin <[email protected]>
Add a label, soc0, to the soc device tree node. Signed-off-by: Matthew Gerlach <[email protected]>
…strings Add the compatible strings for PCIe root port of the Agilex family of chips. Signed-off-by: Matthew Gerlach <[email protected]>
Updating the node name to the fcs_config Signed-off-by: Balsundar Ponnusamy <[email protected]> Reviewed-by: Tanmay Kathpalia <[email protected]> Reviewed-by: Khadgi Sagar <[email protected]> Reviewed-by: Mahesh Rao <[email protected]>
Remove yaml file for the fcs hal driver Signed-off-by: Balsundar Ponnusamy <[email protected]> Reviewed-by: Tanmay Kathpalia <[email protected]> Reviewed-by: Khadgi Sagar <[email protected]> Reviewed-by: Mahesh Rao <[email protected]>
Removing crypto driver and this functionality will be moved to fcs config driver Signed-off-by: Balsundar Ponnusamy <[email protected]> Reviewed-by: Tanmay Kathpalia <[email protected]> Reviewed-by: Khadgi Sagar <[email protected]> Reviewed-by: Mahesh Rao <[email protected]>
…river Implement random number generation using config driver Combine FCS HAL driver into config driver Signed-off-by: Balsundar Ponnusamy <[email protected]> Reviewed-by: Tanmay Kathpalia <[email protected]> Reviewed-by: Khadgi Sagar <[email protected]> Reviewed-by: Mahesh Rao <[email protected]>
…river Enable FCS config driver for compilation Signed-off-by: Balsundar Ponnusamy <[email protected]> Reviewed-by: Tanmay Kathpalia <[email protected]> Reviewed-by: Khadgi Sagar <[email protected]> Reviewed-by: Mahesh Rao <[email protected]>
Fix day one compilation warning for enum vs. int mismatch. Signed-off-by: Matthew Gerlach <[email protected]>
Implement coverity false positive bypass mechanism until proper disposition mechanism is implemented. Signed-off-by: Adrian Ng Ho Yin <[email protected]>
…cores to WFI Add reboot notifier to put all secondary cores to WFI prior to reboot to support warm reset on Agilex and Stratix10. Signed-off-by: Adrian Ng Ho Yin <[email protected]>
Add quirk to disable runtime PM for socfpga. When runtime PM is enabled it will cause the SPL to stall after reboot as SPI is not put into a warm reset state by the kernel. Signed-off-by: Adrian Ng Ho Yin <[email protected]>
… register This fix is required to use the correct altera_read_config type for CVP credit register for Agilex5 and for non-Agilex5. altera_read_config_dword is used for Agilex5 credits as it is 12bits and altera_read_config_byte is used for non-Agilex5 credits as it is 8bits. Signed-off-by: Murugasen Krishnan, Kuhanh <[email protected]>
Update the phy skew value based on the theoretically calculated value, based on the board skew clock (ps) Signed-off-by: Boon Khai Ng <[email protected]>
interrupt support Add Async interrupt support to Stratix10 SoC FPGA Signed-off-by: Mahesh Rao <[email protected]>
Change print log level from warn to debug. Signed-off-by: Mahesh Rao <[email protected]>
OCRAM is initialize by Secure Device Manager(SDM). For the warm reset, SDM do not perform the OCRAM wipe. So OCRAM ECC INITCOMPLETEA bit is not set and ECC_EN bit of CTRL register is required to enable after the warm reset. Signed-off-by: Niravkumar L Rabara <[email protected]>
This patch addresses the SDOS warning that occurs for weak keys. Signed-off-by: Sagar Khadgi <[email protected]> Reviewed-by: Tanmay Kathpalia <[email protected]> Reviewed-by: Khadgi Sagar <[email protected]> Reviewed-by: Mahesh Rao <[email protected]> Reviewed-by: Ang Tien Sung <[email protected]>
…dependency Altera CvP FPGA Manager driver depends on FPGA Configuration Framework drivers to be loaded in the kernel. Updating FPGA_MGR_ALTERA_CVP in Kconfig depends on to include FPGA. Signed-off-by: Murugasen Krishnan, Kuhanh <[email protected]>
Add the base device tree for the Agilex3 SoCDK, which is an instantiation of the Agilex5 Hard Processor System (HPS). Signed-off-by: Niravkumar L Rabara <[email protected]>
Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the n5x device tree. This update configures the SPI controller to use a 4-bit bus width for both transmission and reception, potentially improving SPI throughput and matching the hardware capabilities more closely. Signed-off-by: Fong, Yan Kei <[email protected]>
… width Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the stratix10 device tree. This update configures the SPI controller to use a 4-bit bus width for both transmission and reception, potentially improving SPI throughput and matching the hardware capabilities more closely. Signed-off-by: Fong, Yan Kei <[email protected]>
Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the agilex device tree. This update configures the SPI controller to use a 4-bit bus width for both transmission and reception, potentially improving SPI throughput and matching the hardware capabilities more closely. Signed-off-by: Fong, Yan Kei <[email protected]>
…idth Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the agilex5 device tree. This update configures the SPI controller to use a 4-bit bus width for both transmission and reception, potentially improving SPI throughput and matching the hardware capabilities more closely. Signed-off-by: Fong, Yan Kei <[email protected]>
Remove redundant review check as its enabled in the git inventory settings. Signed-off-by: Adrian Ng Ho Yin <[email protected]>
…id soft error Ensure that the pointer passed to module_put() in spi_nor_put_device() is not NULL before use. In certain configurations, the pointer may be uninitialized or NULL, which can lead to a null pointer dereference and a soft kernel error. This change adds a guard clause to return early, preventing the error and maintaining system stability without requiring a reboot. Signed-off-by: Khairul Anuar Romli <[email protected]>
…node Removed undefined clock in SMMU node which causes smmu probe to fail. Signed-off-by: Adrian Ng Ho Yin <[email protected]>
…ND boot Add new DTS file to update the boot args and flash partition details to accommodate the new FIP partition for ATF direct NAND boot method. Signed-off-by: Girisha Dengi <[email protected]>
The 'no-sdio' property indicates that the controller is limited in sending SDIO commands during initialization. This patch removes the property to enable full SDIO functionality, allowing SDIO peripherals to be properly initialized and used. Signed-off-by: Rohan G Thomas <[email protected]>
When deleting an L3/L4 flower filter entry, the action field is not being reset. So if a filter was previously configured with a drop action, that action may persist and affect subsequent configurations unintentionally. This commit ensures action field is cleared when the filter is deleted. Fixes: 425eabd ("net: stmmac: Implement L3/L4 Filters using TC Flower") Signed-off-by: Rohan G Thomas <[email protected]>
./run_platform_test.sh
Check if tnApcMgr is running; if it is not, uncomment below line and execute the run_platform_test.sh script.
/proj/sw/work/shirish/sdk-build/sdk/sdk/aot-tests/build-fpga/weights.safetensors exists
Running on v0.1.1.tsv36_09_12_2025
[2018-03-09 12:36:07.007] [error] [llama.cpp:14] No expected result file specified, disabling validation.
Usage: %s llama_reference.safetensors
[2018-03-09 12:36:07.015] [info] Build: 2025-08-11 16:35:04 v0.3.5 (687d27e/HEAD) | Type: RelWithDebInfo | Device: FPGA
[2018-03-09 12:36:08.097] [info] [llama.cpp:63] Execution time: 1034 ms
[2018-03-09 12:36:08.097] [info] [llama.cpp:66] [LlamaForCausalLM_Random] No expected result file specified, skipping result validation.
[2018-03-09 12:36:08.145798] 329:330 [error] :: </proj/work/ssaha/tsi_yocto/tsi_yocto_workspace/tsi-apc-manager/platform/rsm_mgr/txe_alloc_release.c:153> Invalid request count (0), must be between 1 and 4096
Profiling Results (LlamaForCausalLM_Random):
------------------------------------------------------------------------------------------------------------------------
Calls Total(ms) T/call Self(ms) Function
------------------------------------------------------------------------------------------------------------------------
- 742.3070 0.0000 742.3070 [64.35%] [Thread] LlamaForCausalLM_Random
1235 344.2040 0.2787 0.0000 └─ [29.84%] tsi::runtime::TsavRT::awaitCommandListCompletion
1235 898.4952 0.7275 898.4952 └─ [77.89%] TXE 0 Idle
1024 387.1096 0.3780 387.1096 └─ [33.56%] [ txe_blob_6 ]
96 48.0055 0.5001 48.0055 └─ [ 4.16%] [ txe_blob_1 ]
8 20.8556 2.6069 20.8556 └─ [ 1.81%] [ txe_blob_11 ]
8 19.1245 2.3906 19.1245 └─ [ 1.66%] [ txe_blob_8 ]
8 18.7089 2.3386 18.7089 └─ [ 1.62%] [ txe_blob_9 ]
8 16.9034 2.1129 16.9034 └─ [ 1.47%] [ txe_blob_10 ]
16 8.5623 0.5351 8.5623 └─ [7.42e-01%] [ txe_blob_7 ]
16 2.9197 0.1825 2.9197 └─ [2.53e-01%] [ txe_blob_5 ]
16 2.9138 0.1821 2.9138 └─ [2.53e-01%] [ txe_blob_3 ]
16 2.8928 0.1808 2.8928 └─ [2.51e-01%] [ txe_blob_2 ]
16 2.8832 0.1802 2.8832 └─ [2.50e-01%] [ txe_blob_4 ]
3 0.9383 0.3128 0.9383 └─ [8.13e-02%] [ txe_blob_0 ]
26145 113.4490 0.0043 113.4490 └─ [ 9.83%] tsi::runtime::TsavRT::stridedCopy
60 89.1400 1.4857 0.6750 └─ [ 7.73%] tsi::runtime::TsavRT::getTensor
60 88.2730 1.4712 88.2730 └─ [ 7.65%] tsi::runtime::memory::SafeTensorsParser::loadTensors
120 0.1920 0.0016 0.1920 └─ [1.66e-02%] tsi::runtime::memory::SafeTensorsParser::getTensorBuffer
1 58.7510 58.7510 56.6850 └─ [ 5.09%] tsi::runtime::TsavRTFPGA::finalize
1 2.0660 2.0660 2.0660 └─ [1.79e-01%] tsi::runtime::TsavRTFPGA::releaseTxes
1 43.4040 43.4040 35.4850 └─ [ 3.76%] tsi::runtime::TsavRTFPGA::initialize
1 3.2840 3.2840 3.2840 └─ [2.85e-01%] tsi::runtime::TsavRTFPGA::initializeQueues
1 3.2270 3.2270 3.2270 └─ [2.80e-01%] tsi::runtime::TsavRT::initialize
1 1.4080 1.4080 1.3710 └─ [1.22e-01%] tsi::runtime::TsavRTFPGA::sendNOPTestCommand
2 0.0370 0.0185 0.0370 └─ [3.21e-03%] tsi::runtime::executeWithTimeout
1235 33.0450 0.0268 30.4520 └─ [ 2.86%] tsi::runtime::TsavRT::finalizeCommandList
1235 2.5930 0.0021 2.5930 └─ [2.25e-01%] tsi::runtime::executeWithTimeout
1235 28.5630 0.0231 28.5630 └─ [ 2.48%] tsi::runtime::TsavRT::addCommandToList
1 17.7130 17.7130 1.3300 └─ [ 1.54%] tsi::runtime::TsavRT::initTensorLoader
1 14.0300 14.0300 14.0300 └─ [ 1.22%] tsi::runtime::memory::SafeTensorsParser::parseJSONHeader
1 2.3530 2.3530 2.3530 └─ [2.04e-01%] tsi::runtime::memory::SafeTensorsParser::SafeTensorsParser
12 5.2460 0.4372 5.2460 └─ [4.55e-01%] tsi::runtime::TsavRTFPGA::loadBlob
767 3.5350 0.0046 3.5350 └─ [3.06e-01%] tsi::runtime::TsavRT::allocate
131 2.3430 0.0179 2.3430 └─ [2.03e-01%] tsi::runtime::TsavRT::copy
826 2.2750 0.0028 2.2750 └─ [1.97e-01%] tsi::runtime::TsavRT::deallocate
12 0.6390 0.0533 0.6390 └─ [5.54e-02%] tsi::runtime::TsavRTFPGA::unloadBlob
------------------------------------------------------------------------------------------------------------------------
[Thread] tsi::runtime::TsavRT::processResponses (cumulative over all threads)
------------------------------------------------------------------------------------------------------------------------
1235 307.0510 0.2486 9.1620 [26.62%] [Thread] tsi::runtime::TsavRT::processResponses
1235 297.8890 0.2412 297.8890 └─ [25.82%] tsi::runtime::executeWithTimeout
========================================================================================================================
- 1153.5590 0.0000 1153.5590 [100.00%] TOTAL
========================================================================================================================
Counter Metrics:
------------------------------------------------------------------------------------------------------------------------
Metric Min Max Avg
------------------------------------------------------------------------------------------------------------------------
Queue_0_Occupancy 0.0000 1.0000 0.9984
------------------------------------------------------------------------------------------------------------------------
my cat's name is Luna.
llama_perf_sampler_print: sampling time = 110.77 ms / 11 runs ( 10.07 ms per token, 99.31 tokens per second)
llama_perf_context_print: load time = 88830.83 ms
llama_perf_context_print: prompt eval time = 43453.76 ms / 6 tokens ( 7242.29 ms per token, 0.14 tokens per second)
llama_perf_context_print: eval time = 121525.86 ms / 4 runs (30381.46 ms per token, 0.03 tokens per second)
llama_perf_context_print: total time = 210497.30 ms / 10 tokens
=== GGML Perf Summary ===
Op Runs Total us Avg us
ADD 220 989557 4497.99
MUL 335 1355105 4045.09
RMS_NORM 734 55200 75.20
MUL_MAT 3465 417486527 120486.73
CPY 641 33326 51.99
CONT 271 3196 11.79
RESHAPE 935 10881 11.64
VIEW 717 1134 1.58
PERMUTE 716 1076 1.50
TRANSPOSE 175 486 2.78
GET_ROWS 46 23306 506.65
SOFT_MAX 301 58907 195.70
ROPE 770 67855 88.12
UNARY 110 502841 4571.28
-> SILU 110 502841 4571.28
[2018-03-09 12:39:41.428105] 329:330 [error] :: </proj/work/ssaha/tsi_yocto/tsi_yocto_workspace/tsi-apc-manager/platform/rsm_mgr/txe_alloc_release.c:153> Invalid request count (0), must be between 1 and 4096
OPU Profiling Results:
------------------------------------------------------------------------------------------------------------------------
Calls Total(ms) T/call Self(ms) Function
------------------------------------------------------------------------------------------------------------------------
1 152.0770 152.0770 34.6630 [9.04e-02%] [Thread] OPU
1 117.4140 117.4140 96.1060 └─ [6.98e-02%] tsi::runtime::TsavRTFPGA::initialize
1 9.2100 9.2100 9.2100 └─ [5.48e-03%] tsi::runtime::TsavRTFPGA::initializeQueues
1 8.7220 8.7220 8.7220 └─ [5.19e-03%] tsi::runtime::TsavRT::initialize
1 3.3760 3.3760 2.8580 └─ [2.01e-03%] tsi::runtime::TsavRTFPGA::sendNOPTestCommand
2 0.5180 0.2590 0.5180 └─ [3.08e-04%] tsi::runtime::executeWithTimeout
------------------------------------------------------------------------------------------------------------------------
[Thread] tsi::runtime::TsavRT::awaitCommandListCompletion (cumulative over all threads)
------------------------------------------------------------------------------------------------------------------------
1195 1074.6440 0.8993 0.0000 [6.39e-01%] [Thread] tsi::runtime::TsavRT::awaitCommandListCompletion
1195 3.29e+05 275.1446 3.29e+05 └─ [195.50%] TXE 0 Idle
655 592.6633 0.9048 592.6633 └─ [3.52e-01%] [ txe_mult ]
110 320.6818 2.9153 320.6818 └─ [1.91e-01%] [ txe_silu ]
430 274.6878 0.6388 274.6878 └─ [1.63e-01%] [ txe_add ]
------------------------------------------------------------------------------------------------------------------------
[Thread] tsi::runtime::TsavRT::finalizeCommandList (cumulative over all threads)
------------------------------------------------------------------------------------------------------------------------
1195 867.2310 0.7257 827.2830 [5.16e-01%] [Thread] tsi::runtime::TsavRT::finalizeCommandList
1195 39.9480 0.0334 39.9480 └─ [2.38e-02%] tsi::runtime::executeWithTimeout
------------------------------------------------------------------------------------------------------------------------
[Thread] tsi::runtime::TsavRT::processResponses (cumulative over all threads)
------------------------------------------------------------------------------------------------------------------------
1195 1548.9540 1.2962 56.4450 [9.21e-01%] [Thread] tsi::runtime::TsavRT::processResponses
1195 1492.5090 1.2490 1492.5090 └─ [8.87e-01%] tsi::runtime::executeWithTimeout
------------------------------------------------------------------------------------------------------------------------
[Thread] tsi::runtime::TsavRTFPGA::finalize (cumulative over all threads)
------------------------------------------------------------------------------------------------------------------------
1 70.2460 70.2460 60.8160 [4.18e-02%] [Thread] tsi::runtime::TsavRTFPGA::finalize
1 9.4300 9.4300 9.4300 └─ [5.61e-03%] tsi::runtime::TsavRTFPGA::releaseTxes
------------------------------------------------------------------------------------------------------------------------
[Thread] tsi::runtime::TsavRT::allocate (cumulative over all threads)
------------------------------------------------------------------------------------------------------------------------
1196 75.3060 0.0630 75.3060 [4.48e-02%] [Thread] tsi::runtime::TsavRT::allocate
------------------------------------------------------------------------------------------------------------------------
[Thread] tsi::runtime::TsavRTFPGA::loadBlob (cumulative over all threads)
------------------------------------------------------------------------------------------------------------------------
1195 415.2100 0.3475 415.2100 [2.47e-01%] [Thread] tsi::runtime::TsavRTFPGA::loadBlob
------------------------------------------------------------------------------------------------------------------------
[Thread] tsi::runtime::TsavRT::addCommandToList (cumulative over all threads)
------------------------------------------------------------------------------------------------------------------------
1195 69.5420 0.0582 69.5420 [4.13e-02%] [Thread] tsi::runtime::TsavRT::addCommandToList
------------------------------------------------------------------------------------------------------------------------
[Thread] tsi::runtime::TsavRTFPGA::unloadBlob (cumulative over all threads)
------------------------------------------------------------------------------------------------------------------------
1195 91.4560 0.0765 91.4560 [5.44e-02%] [Thread] tsi::runtime::TsavRTFPGA::unloadBlob
------------------------------------------------------------------------------------------------------------------------
[Thread] tsi::runtime::TsavRT::deallocate (cumulative over all threads)
------------------------------------------------------------------------------------------------------------------------
1195 18.9050 0.0158 18.9050 [1.12e-02%] [Thread] tsi::runtime::TsavRT::deallocate
========================================================================================================================
- 1.68e+05 0.0000 1.68e+05 [100.00%] TOTAL
========================================================================================================================
Counter Metrics:
------------------------------------------------------------------------------------------------------------------------
Metric Min Max Avg
------------------------------------------------------------------------------------------------------------------------
Queue_0_Occupancy 0.0000 1.0000 0.6951
------------------------------------------------------------------------------------------------------------------------
@FIR-972: Update 6.12.19 LTS
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Description: <Description the change of this Pull Request. Include HSD#, related Pull Request>
Impact Analysis:
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Regression Test result: <Regtest result link .>