Skip to content

[Coroutines] ABI Object #5

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Closed
wants to merge 43 commits into from
Closed

[Coroutines] ABI Object #5

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
43 commits
Select commit Hold shift + click to select a range
6be9be5
[LLD][COFF][NFC] Store live flag in ImportThunkChunk. (#108459)
cjacek Sep 13, 2024
387bee9
[llvm][unittests] Strip unneeded uses of raw_string_ostream::str() (NFC)
JOE1994 Sep 13, 2024
69a2115
[DAG] Fold trunc(srl(extract_elt(vec,c1),c2)) -> extract_elt(bitcast(…
RKSimon Sep 13, 2024
a3ea018
[X86] Use MCRegister in X86AsmParser. (#108509)
topperc Sep 13, 2024
ee4582f
[RISCV] Use CCValAssign::getCustomReg for fixed vector arguments/retu…
topperc Sep 13, 2024
4a9b6b0
[X86] Cleanup lowerShuffleToEXPAND arg layout. NFC.
RKSimon Sep 11, 2024
326287f
Add missing FillOp to winograd lowering (#108181)
RoboTux Sep 13, 2024
387ef59
[clang][TableGen] Change TypeNodesEmitter to use const RecordKeeper (…
jurahul Sep 13, 2024
f637273
[clang][TableGen] Change SACheckersEmitter to use const RecordKeeper …
jurahul Sep 13, 2024
d757bbf
[clang][TableGen] Change SyntaxEmitter to use const RecordKeeper (#10…
jurahul Sep 13, 2024
75d8724
[clang][TableGen] Change MVE Emitter to use const RecordKeeper (#108500)
jurahul Sep 13, 2024
a4b1617
[clang][TableGen] Change NeonEmitter to use const RecordKeeper (#108501)
jurahul Sep 13, 2024
974fa85
[clang][TableGen] Change RISCVVEmitter to use const RecordKeeper (#10…
jurahul Sep 13, 2024
ab06a18
[IRSim] Avoid repeated hash lookups (NFC) (#108483)
kazutakahirata Sep 13, 2024
711278e
[clang][TableGen] Change SVE Emitter to use const RecordKeeper (#108503)
jurahul Sep 13, 2024
99fe595
[libc] implement clock_gettime using vDSO (#108458)
SchrodingerZhu Sep 13, 2024
ea5d37f
[LLD][COFF] Add Support for ARM64EC Import Thunks (#108460)
cjacek Sep 13, 2024
a643836
[libc] fix build issue in overlay mode (#108583)
SchrodingerZhu Sep 13, 2024
ff1de24
[llvm-exegesis] Remove getter for RegNameToRegNo mapping
boomanaiden154 Sep 13, 2024
ffeb793
[clang][analyzer][docs] Fix documentation of checker 'StackAddrAsyncE…
balazske Sep 13, 2024
213c59d
[lldb] Add pc check for thread-step-by-bp algorithms (#108504)
jasonmolenda Sep 13, 2024
65a4d11
[lldb] Set the stop reason when receiving swbreak/hwbreak (#108518)
jasonmolenda Sep 13, 2024
51f5525
[libc++][NFC] Mark P1869R1 as implemented (#107746)
H-G-Hristov Sep 13, 2024
82987bd
[libc] fix dependency path for vDSO (#108591)
SchrodingerZhu Sep 13, 2024
cd6844c
[PowerPC][NFC] autogen mma tc checks via update_cc_test_checks (#108584)
lei137 Sep 13, 2024
661382f
[LLDB][Minidump] Minidump erase file on failure (#108259)
Jlalond Sep 13, 2024
f0f1b70
[SandboxIR][PassRegistry] Parse pipeline string (#108103)
Sep 13, 2024
8e2843b
[RISCV][Docs] Change Zvbb and Zvkb from 'Assembly Support' to Support…
topperc Sep 13, 2024
f902339
Adjust modulemap to mark mm3dnow as textual header. (#107155)
jyknight Sep 13, 2024
fffc7fb
[SandboxIR] Implement DSOLocalEquivalent (#108473)
Sep 13, 2024
02e4186
[X86] AMD Zen 5 Initial enablement (#107964)
ganeshgit Sep 13, 2024
b9d85b1
[CodeGen] Use DenseMap::operator[] (NFC) (#108489)
kazutakahirata Sep 13, 2024
4ef16e3
[NFC][clang-tidy] document fix to bugprone-return-const-ref-from-para…
5chmidti Sep 13, 2024
a953982
[mlir][GPU] Plumb range information through the NVVM lowerings (#107659)
krzysz00 Sep 13, 2024
02d8813
Add a comment in the SB API doc about keeping the SB API's lightweigh…
jimingham Sep 13, 2024
b6bf27e
Avoid expression evaluation in libStdC++ std::vector<bool> synthetic …
jeffreytan81 Sep 13, 2024
0351dc5
[lldb] Do not use LC_FUNCTION_STARTS data to determine symbol size as…
bulbazord Sep 13, 2024
3a27458
[LiveDebugValues] Avoid repeated hash lookups (NFC) (#108484)
kazutakahirata Sep 13, 2024
7582308
[AArch64][GISel] Scalarize i128 vector shifts.
davemgreen Sep 13, 2024
3a4b30e
[AArch64][GISel] Scalarize i128 ICmp and Select.
davemgreen Sep 13, 2024
d4f41be
[Utils] add update-verify-tests.py (#97369)
hnrklssn Sep 13, 2024
4c040c0
[Coroutines] Move Shape to its own header (#108242)
Sep 13, 2024
ba9e523
[Coroutines] Refactor CoroShape::buildFrom to support ABI
Aug 24, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
9 changes: 9 additions & 0 deletions ...tools-extra/docs/clang-tidy/checks/bugprone/return-const-ref-from-parameter.rst
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,15 @@ after the call. When the function returns such a parameter also as constant refe
then the returned reference can be used after the object it refers to has been
destroyed.

This issue can be resolved by declaring an overload of the problematic function
where the ``const &`` parameter is instead declared as ``&&``. The developer has
to ensure that the implementation of that function does not produce a
use-after-free, the exact error that this check is warning against.
Marking such an ``&&`` overload as ``deleted``, will silence the warning as
well. In the case of different ``const &`` parameters being returned depending
on the control flow of the function, an overload where all problematic
``const &`` parameters have been declared as ``&&`` will resolve the issue.

Example
-------

Expand Down
4 changes: 2 additions & 2 deletions clang/docs/analyzer/checkers.rst
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2571,8 +2571,8 @@ with the `offsetof` macro.

.. _alpha-core-StackAddressAsyncEscape:

alpha.core.StackAddressAsyncEscape (C)
""""""""""""""""""""""""""""""""""""""
alpha.core.StackAddressAsyncEscape (ObjC)
"""""""""""""""""""""""""""""""""""""""""
Check that addresses to stack memory do not escape the function that involves dispatch_after or dispatch_async.
This checker is a part of ``core.StackAddressEscape``, but is temporarily disabled until some false positives are fixed.

Expand Down
4 changes: 4 additions & 0 deletions clang/lib/Basic/Targets/X86.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -728,6 +728,9 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
case CK_ZNVER4:
defineCPUMacros(Builder, "znver4");
break;
case CK_ZNVER5:
defineCPUMacros(Builder, "znver5");
break;
case CK_Geode:
defineCPUMacros(Builder, "geode");
break;
Expand Down Expand Up @@ -1626,6 +1629,7 @@ std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
case CK_ZNVER2:
case CK_ZNVER3:
case CK_ZNVER4:
case CK_ZNVER5:
// Deprecated
case CK_x86_64:
case CK_x86_64_v2:
Expand Down
6 changes: 2 additions & 4 deletions clang/lib/Headers/module.modulemap
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -66,6 +66,8 @@ module _Builtin_intrinsics [system] [extern_c] {
textual header "__wmmintrin_aes.h"
textual header "__wmmintrin_pclmul.h"

textual header "mm3dnow.h"

explicit module mm_malloc {
requires !freestanding
header "mm_malloc.h"
Expand Down Expand Up @@ -122,10 +124,6 @@ module _Builtin_intrinsics [system] [extern_c] {
header "popcntintrin.h"
}

explicit module mm3dnow {
header "mm3dnow.h"
}

explicit module aes_pclmul {
header "wmmintrin.h"
export aes
Expand Down
68 changes: 68 additions & 0 deletions clang/test/CodeGen/PowerPC/builtins-ppc-build-pair-mma.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,8 @@
// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-LE
// RUN: %clang_cc1 -O3 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-BE
// RUN: %clang_cc1 -O0 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-LE-NOOPT

// CHECK-LE-LABEL: @test1(
// CHECK-LE-NEXT: entry:
Expand All @@ -16,6 +18,42 @@
// CHECK-BE-NEXT: store <512 x i1> [[TMP0]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2:![0-9]+]]
// CHECK-BE-NEXT: ret void
//
// CHECK-LE-NOOPT-LABEL: @test1(
// CHECK-LE-NOOPT-NEXT: entry:
// CHECK-LE-NOOPT-NEXT: [[VQP_ADDR:%.*]] = alloca ptr, align 8
// CHECK-LE-NOOPT-NEXT: [[VPP_ADDR:%.*]] = alloca ptr, align 8
// CHECK-LE-NOOPT-NEXT: [[VC1_ADDR:%.*]] = alloca <16 x i8>, align 16
// CHECK-LE-NOOPT-NEXT: [[VC2_ADDR:%.*]] = alloca <16 x i8>, align 16
// CHECK-LE-NOOPT-NEXT: [[VC3_ADDR:%.*]] = alloca <16 x i8>, align 16
// CHECK-LE-NOOPT-NEXT: [[VC4_ADDR:%.*]] = alloca <16 x i8>, align 16
// CHECK-LE-NOOPT-NEXT: [[RESP_ADDR:%.*]] = alloca ptr, align 8
// CHECK-LE-NOOPT-NEXT: [[VQ:%.*]] = alloca <512 x i1>, align 64
// CHECK-LE-NOOPT-NEXT: [[VP:%.*]] = alloca <256 x i1>, align 32
// CHECK-LE-NOOPT-NEXT: [[RES:%.*]] = alloca <512 x i1>, align 64
// CHECK-LE-NOOPT-NEXT: store ptr [[VQP:%.*]], ptr [[VQP_ADDR]], align 8
// CHECK-LE-NOOPT-NEXT: store ptr [[VPP:%.*]], ptr [[VPP_ADDR]], align 8
// CHECK-LE-NOOPT-NEXT: store <16 x i8> [[VC1:%.*]], ptr [[VC1_ADDR]], align 16
// CHECK-LE-NOOPT-NEXT: store <16 x i8> [[VC2:%.*]], ptr [[VC2_ADDR]], align 16
// CHECK-LE-NOOPT-NEXT: store <16 x i8> [[VC3:%.*]], ptr [[VC3_ADDR]], align 16
// CHECK-LE-NOOPT-NEXT: store <16 x i8> [[VC4:%.*]], ptr [[VC4_ADDR]], align 16
// CHECK-LE-NOOPT-NEXT: store ptr [[RESP:%.*]], ptr [[RESP_ADDR]], align 8
// CHECK-LE-NOOPT-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VQP_ADDR]], align 8
// CHECK-LE-NOOPT-NEXT: [[TMP1:%.*]] = load <512 x i1>, ptr [[TMP0]], align 64
// CHECK-LE-NOOPT-NEXT: store <512 x i1> [[TMP1]], ptr [[VQ]], align 64
// CHECK-LE-NOOPT-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VPP_ADDR]], align 8
// CHECK-LE-NOOPT-NEXT: [[TMP3:%.*]] = load <256 x i1>, ptr [[TMP2]], align 32
// CHECK-LE-NOOPT-NEXT: store <256 x i1> [[TMP3]], ptr [[VP]], align 32
// CHECK-LE-NOOPT-NEXT: [[TMP4:%.*]] = load <16 x i8>, ptr [[VC1_ADDR]], align 16
// CHECK-LE-NOOPT-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[VC2_ADDR]], align 16
// CHECK-LE-NOOPT-NEXT: [[TMP6:%.*]] = load <16 x i8>, ptr [[VC3_ADDR]], align 16
// CHECK-LE-NOOPT-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr [[VC4_ADDR]], align 16
// CHECK-LE-NOOPT-NEXT: [[TMP8:%.*]] = call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> [[TMP7]], <16 x i8> [[TMP6]], <16 x i8> [[TMP5]], <16 x i8> [[TMP4]])
// CHECK-LE-NOOPT-NEXT: store <512 x i1> [[TMP8]], ptr [[RES]], align 64
// CHECK-LE-NOOPT-NEXT: [[TMP9:%.*]] = load <512 x i1>, ptr [[RES]], align 64
// CHECK-LE-NOOPT-NEXT: [[TMP10:%.*]] = load ptr, ptr [[RESP_ADDR]], align 8
// CHECK-LE-NOOPT-NEXT: store <512 x i1> [[TMP9]], ptr [[TMP10]], align 64
// CHECK-LE-NOOPT-NEXT: ret void
//
void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc1, vector unsigned char vc2,
vector unsigned char vc3, vector unsigned char vc4, unsigned char *resp) {
__vector_quad vq = *((__vector_quad *)vqp);
Expand All @@ -37,6 +75,36 @@ void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc1, vec
// CHECK-BE-NEXT: store <256 x i1> [[TMP0]], ptr [[RESP:%.*]], align 32, !tbaa [[TBAA6:![0-9]+]]
// CHECK-BE-NEXT: ret void
//
// CHECK-LE-NOOPT-LABEL: @test2(
// CHECK-LE-NOOPT-NEXT: entry:
// CHECK-LE-NOOPT-NEXT: [[VQP_ADDR:%.*]] = alloca ptr, align 8
// CHECK-LE-NOOPT-NEXT: [[VPP_ADDR:%.*]] = alloca ptr, align 8
// CHECK-LE-NOOPT-NEXT: [[VC1_ADDR:%.*]] = alloca <16 x i8>, align 16
// CHECK-LE-NOOPT-NEXT: [[VC2_ADDR:%.*]] = alloca <16 x i8>, align 16
// CHECK-LE-NOOPT-NEXT: [[RESP_ADDR:%.*]] = alloca ptr, align 8
// CHECK-LE-NOOPT-NEXT: [[VQ:%.*]] = alloca <512 x i1>, align 64
// CHECK-LE-NOOPT-NEXT: [[VP:%.*]] = alloca <256 x i1>, align 32
// CHECK-LE-NOOPT-NEXT: [[RES:%.*]] = alloca <256 x i1>, align 32
// CHECK-LE-NOOPT-NEXT: store ptr [[VQP:%.*]], ptr [[VQP_ADDR]], align 8
// CHECK-LE-NOOPT-NEXT: store ptr [[VPP:%.*]], ptr [[VPP_ADDR]], align 8
// CHECK-LE-NOOPT-NEXT: store <16 x i8> [[VC1:%.*]], ptr [[VC1_ADDR]], align 16
// CHECK-LE-NOOPT-NEXT: store <16 x i8> [[VC2:%.*]], ptr [[VC2_ADDR]], align 16
// CHECK-LE-NOOPT-NEXT: store ptr [[RESP:%.*]], ptr [[RESP_ADDR]], align 8
// CHECK-LE-NOOPT-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VQP_ADDR]], align 8
// CHECK-LE-NOOPT-NEXT: [[TMP1:%.*]] = load <512 x i1>, ptr [[TMP0]], align 64
// CHECK-LE-NOOPT-NEXT: store <512 x i1> [[TMP1]], ptr [[VQ]], align 64
// CHECK-LE-NOOPT-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VPP_ADDR]], align 8
// CHECK-LE-NOOPT-NEXT: [[TMP3:%.*]] = load <256 x i1>, ptr [[TMP2]], align 32
// CHECK-LE-NOOPT-NEXT: store <256 x i1> [[TMP3]], ptr [[VP]], align 32
// CHECK-LE-NOOPT-NEXT: [[TMP4:%.*]] = load <16 x i8>, ptr [[VC1_ADDR]], align 16
// CHECK-LE-NOOPT-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[VC2_ADDR]], align 16
// CHECK-LE-NOOPT-NEXT: [[TMP6:%.*]] = call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[TMP5]], <16 x i8> [[TMP4]])
// CHECK-LE-NOOPT-NEXT: store <256 x i1> [[TMP6]], ptr [[RES]], align 64
// CHECK-LE-NOOPT-NEXT: [[TMP7:%.*]] = load <256 x i1>, ptr [[RES]], align 32
// CHECK-LE-NOOPT-NEXT: [[TMP8:%.*]] = load ptr, ptr [[RESP_ADDR]], align 8
// CHECK-LE-NOOPT-NEXT: store <256 x i1> [[TMP7]], ptr [[TMP8]], align 32
// CHECK-LE-NOOPT-NEXT: ret void
//
void test2(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc1,
vector unsigned char vc2, unsigned char *resp) {
__vector_quad vq = *((__vector_quad *)vqp);
Expand Down
Loading