⚡ Power-Optimized 3-Stage Pipelined RISC-V Processor

This project is a complete design and implementation of a 3-stage pipelined RISC-V processor in Verilog HDL, optimized for energy-efficient computing. The design integrates enable control, latch-based clock gating, and data gating to minimize dynamic power consumption while preserving throughput—making it highly suitable for low-power IoT and embedded applications.

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🚀 Key Features

• 3-Stage Pipeline: Instruction Fetch, Decode, Execute.

• Power Optimization Techniques:

  • Enable Control
  • Latch-Based Clock Gating
  • Data Gating

• Energy Efficiency: Reduced dynamic power from 0.71 W → 0.03 W.

• Implementation: Designed in Verilog HDL, verified via simulation, and tested on FPGA.

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🏗️ Architecture Overview

• Top-Level (pipeline.v): Integrates all processor stages.
• Instruction Memory & Fetch Unit: Supplies instructions to the pipeline.
• Instruction Decoder: Decodes RISC-V instructions for execution.
• Execute Unit: Performs ALU operations and branching.
• Clock Gating Module: Applies enable-control and latch-based gating.
• Pipeline Registers: Preserve state across stages with power-aware design.

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⚡ Power Optimization Results

Design Version	Dynamic Power
3-Stage RISC-V (Baseline)	0.71 W
3-Stage RISC-V Pipelined	0.63 W
Pipeline with Enable Control	0.13 W
Pipeline with Latch-Based Clock Gating	0.10 W
Pipeline with Data Gating	0.03 W

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📁 Project Structure

power-optimized-riscv/
├── src/
│   ├── clock_gating.v
│   ├── instruction_memory.v
│   ├── instruction_fetch.v
│   ├── instruction_decoder.v
│   ├── execute.v
│   └── pipeline.v
├── test/
│   └── testbench.v
└── README.md

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🛠 Tools Used

• EDA Playground – Simulation & Verification
• Xilinx Vivado – FPGA Synthesis & Power Analysis
• Verilog HDL – Hardware Description Language

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🧪 Verification

The provided testbench validates:

• Correct pipeline execution
• Functional correctness of enable-control & clock gating
• Power reduction efficiency

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👨‍💻 Authors

• M. Pavan Kumar
• P. V. Satya Bala
• M. Sai Likhith
• M. Divya Teja

📜 License: MIT License – Free to use and modify for educational or research purposes.